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Dielectric device, dielectric memory and method of fabricating the same

Assignee: FOOTHILLS IP LLC
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Filing: 1998-06-15
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Granted: 2001-02-27
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Expires: 2018-06-15
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Abstract

Abstract A gate insulating layer and a first lower electrode are formed on a channel region of a silicon substrate, and an interlayer insulating film is formed on the silicon substrate so as to cover the first lower electrode and the gate insulating film. A buffer layer is formed on the interlayer insulating film, and a contact hole is formed in the interlayer insulating film and the buffer layer on the first lower electrode. A connecting layer and a second lower electrode are formed in the contact hole. A ferroelectric thin film and an upper electrode are formed in this order on the buffer layer so as to be brought into contact with the upper surface of the second lower electrode.

Inventors

  • 👤 Satoru Ogasahara
  • 👤 Mitsuaki Harada
  • 👤 Hiroaki Furukawa
  • 👤 Takashi Goto
  • 👤 Tatsuro Gueshi
  • 👤 Yoshiyuki Ishizuka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 01:40
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D30/00; H10D30/60; H10D30/701

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 129 words
A dielectric memory comprising: first and second impurity regions formed with predetermined spacing in a semiconductor; a gate insulating film formed on a region between said first and second impurity regions; a first lower electrode layer formed on said gate insulating film; an interlayer insulating film formed on said semiconductor so as to cover said first lower electrode layer and said gate insulating film and having a contact hole; a second lower electrode layer formed in said contact hole of said interlayer insulating film and electrically connected to said first lower electrode layer; a dielectric film formed on said interlayer insulating film so as to be brought into contact with the upper surface of said second lower electrode layer; and an upper electrode layer formed on said dielectric film.
Claim 2
Dependent Claim 129 words
A dielectric memory comprising: first and second impurity regions formed with predetermined spacing in a semiconductor; a gate insulating film formed on a region between said first and second impurity regions; a first lower electrode layer formed on said gate insulating film; an interlayer insulating film formed on said semiconductor so as to cover said first lower electrode layer and said gate insulating film and having a contact hole; a second lower electrode layer formed in said contact hole of said interlayer insulating film and electrically connected to said first lower electrode layer; a dielectric film formed on said interlayer insulating film so as to be brought into contact with the upper surface of said second lower electrode layer; and an upper electrode layer formed on said dielectric film.
Claim 3
Dependent Claim 38 words
The dielectric memory according to claim 1 , further comprising a connecting layer formed under said second lower electrode layer in said contact hole for electrically connecting said second lower electrode layer to said first lower electrode layer.
Claim 4
Dependent Claim 19 words
The dielectric memory according to claim 1 , further comprising a buffer layer formed on said interlayer insulating film.
Claim 5
Dependent Claim 16 words
The dielectric memory according to claim 1 , wherein said dielectric film is a ferroelectric film.
Claim 6
Dependent Claim 17 words
The dielectric memory according to claim 4 , wherein said ferroelectric film has a perovskite crystal structure.
Claim 7
Independent Claim 127 words
A method of fabricating a dielectric memory, comprising the steps of: forming a gate insulating film on a channel region; forming a first lower electrode layer on said gate insulating film; forming an interlayer insulating film so as to cover said first lower electrode layer and said gate insulating film; forming a contact hole in said interlayer insulating film; forming a second lower electrode layer electrically connected to said first lower electrode layer in said contact hole of said interlayer insulating film; forming a dielectric film on said interlayer insulating film so as to be brought into contact with the upper surface of said second lower electrode layer; forming an upper electrode layer on said dielectric film; and patterning said upper electrode layer and said dielectric film.
Claim 8
Independent Claim 127 words
A method of fabricating a dielectric memory, comprising the steps of: forming a gate insulating film on a channel region; forming a first lower electrode layer on said gate insulating film; forming an interlayer insulating film so as to cover said first lower electrode layer and said gate insulating film; forming a contact hole in said interlayer insulating film; forming a second lower electrode layer electrically connected to said first lower electrode layer in said contact hole of said interlayer insulating film; forming a dielectric film on said interlayer insulating film so as to be brought into contact with the upper surface of said second lower electrode layer; forming an upper electrode layer on said dielectric film; and patterning said upper electrode layer and said dielectric film.
Claim 9
Dependent Claim 47 words
The method according to claim 6 , wherein the step of forming said second lower electrode layer comprises the steps of forming a connecting layer up to a predetermined depth of said contact hole, and forming an electrode layer on said connecting layer in said contact hole.
Claim 10
Dependent Claim 21 words
The method according to claim 7 , further comprising the steps of: forming a diffusion barrier layer on said connecting layer.
Claim 11
Dependent Claim 18 words
The method according to claim 6 , further comprising: forming a buffer layer on said interlayer insulating film.
Claim 12
Dependent Claim 15 words
The method according to claim 6 , wherein said dielectric film is a ferroelectric film.
Claim 13
Dependent Claim 16 words
The method according to claim 10 , wherein said ferroelectric film has a perovskite crystal structure.

References Cited (Backward Citations)

JPH05327062A Cited
EP0697720A1 Cited
JPH0888334A Cited
US5652446A Cited
US5731608A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-02-27 2004-08-28 2005-02-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-02-27 2008-08-28 2009-02-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-02-27 2012-08-28 2013-02-27 $7700.00 Window Closed / Lapsed

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