Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon

Claim 1

A method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with said gate having low resistivity, said MOSFET having a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and said MOSFET initially having a gate comprised of silicide on polysilicon disposed on a gate dielectric over said channel region, the method including steps of: A. depositing a first dielectric layer over said drain region, said source region, and said gate; B. etching away a portion of said first dielectric layer by patterning a photoresist layer deposited on said first dielectric layer to form additional peaks in said first dielectric layer from said etching away of said portion of said first dielectric layer near said gate, and then polishing down said first dielectric layer over said drain region and said source region, and polishing down said first dielectric layer over said gate until one of said silicide on said polysilicon and said polysilicon of said gate is exposed; C. etching away said silicide on said polysilicon and a predetermined thickness of said polysilicon if said silicide is exposed after said step B, and etching away said predetermined thickness of said polysilicon if said polysilicon is exposed after said step B, such that an opening is formed on top of a remaining portion of said polysilicon, said opening having at least one sidewall of an insulating material and having a bottom wall of said remaining portion of said polysilicon; D. depositing a metal within said opening and on said first dielectric layer; and E. polishing down said metal deposited in said step D such that said metal is polished away from said first dielectric layer with said metal being contained within said opening.

Claim 2

A method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with said gate having low resistivity, said MOSFET having a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and said MOSFET initially having a gate comprised of silicide on polysilicon disposed on a gate dielectric over said channel region, the method including steps of: A. depositing a first dielectric layer over said drain region, said source region, and said gate; B. etching away a portion of said first dielectric layer by patterning a photoresist layer deposited on said first dielectric layer to form additional peaks in said first dielectric layer from said etching away of said portion of said first dielectric layer near said gate, and then polishing down said first dielectric layer over said drain region and said source region, and polishing down said first dielectric layer over said gate until one of said silicide on said polysilicon and said polysilicon of said gate is exposed; C. etching away said silicide on said polysilicon and a predetermined thickness of said polysilicon if said silicide is exposed after said step B, and etching away said predetermined thickness of said polysilicon if said polysilicon is exposed after said step B, such that an opening is formed on top of a remaining portion of said polysilicon, said opening having at least one sidewall of an insulating material and having a bottom wall of said remaining portion of said polysilicon; D. depositing a metal within said opening and on said first dielectric layer; and E. polishing down said metal deposited in said step D such that said metal is polished away from said first dielectric layer with said metal being contained within said opening.

Claim 12

A method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with said gate having low resistivity, said MOSFET having a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and said MOSFET initially having a gate comprised of silicide on polysilicon disposed on a gate dielectric over said channel region, the method including steps of: A. depositing an etch stop layer over said drain region, said source region, and said gate; B. depositing a first dielectric layer over said etch stop layer; C. etching away a portion of said first dielectric layer by patterning a photoresist layer deposited on said first dielectric layer to form additional peaks from said etching away of said portion of said first dielectric layer in said first dielectric layer near said gate; D. polishing down said first dielectric layer over said drain region and said source region, and polishing down said first dielectric layer over said gate until one of said silicide on said polysilicon and said polysilicon of said gate is exposed; E. etching away said silicide on said polysilicon and a predetermined thickness of said polysilicon if said silicide is exposed after said step B, and etching away said predetermined thickness of said polysilicon if said polysilicon is exposed after said step B, such that an opening is formed on top of a remaining portion of said polysilicon, said opening having at least one sidewall of an insulating material and having a bottom wall of said remaining portion of said polysilicon; F. implanting dopant into said remaining portion of said polysilicon; G. depositing a metal adhesion layer on said at least one side wall of said opening and on top of said remaining portion of said polysilicon; H. depositing a metal within said opening and on said first dielectric layer; I. polishing down said metal deposited in said step H such that said metal is polished away from said first dielectric layer with said metal being contained within said opening; J. depositing a second dielectric layer over said first dielectric layer and over said metal contained within said opening; and K. forming metal interconnect to said metal contained within said opening; and wherein said remaining portion of said polysilicon has a sufficient thickness such that a threshold voltage of said MOSFET is not substantially affected by said metal disposed on top of said remaining portion of said polysilicon.

Claim 13

A method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with said gate having low resistivity, said MOSFET having a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and said MOSFET initially having a gate comprised of silicide on polysilicon disposed on a gate dielectric over said channel region, the method including steps of: A. depositing an etch stop layer over said drain region, said source region, and said gate; B. depositing a first dielectric layer over said etch stop layer; C. etching away a portion of said first dielectric layer by patterning a photoresist layer deposited on said first dielectric layer to form additional peaks from said etching away of said portion of said first dielectric layer in said first dielectric layer near said gate; D. polishing down said first dielectric layer over said drain region and said source region, and polishing down said first dielectric layer over said gate until one of said silicide on said polysilicon and said polysilicon of said gate is exposed; E. etching away said silicide on said polysilicon and a predetermined thickness of said polysilicon if said silicide is exposed after said step B, and etching away said predetermined thickness of said polysilicon if said polysilicon is exposed after said step B, such that an opening is formed on top of a remaining portion of said polysilicon, said opening having at least one sidewall of an insulating material and having a bottom wall of said remaining portion of said polysilicon; F. implanting dopant into said remaining portion of said polysilicon; G. depositing a metal adhesion layer on said at least one side wall of said opening and on top of said remaining portion of said polysilicon; H. depositing a metal within said opening and on said first dielectric layer; I. polishing down said metal deposited in said step H such that said metal is polished away from said first dielectric layer with said metal being contained within said opening; J. depositing a second dielectric layer over said first dielectric layer and over said metal contained within said opening; and K. forming metal interconnect to said metal contained within said opening; and wherein said remaining portion of said polysilicon has a sufficient thickness such that a threshold voltage of said MOSFET is not substantially affected by said metal disposed on top of said remaining portion of said polysilicon.