US6187615B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip scale packages and methods for manufacturing the chip scale packages at wafer level
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-12-28
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Granted: 2001-02-13
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Expires: 2018-12-28
Abstract
Abstract In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.
Inventors
- 👤 Nam Seog Kim
- 👤 Dong Hyeon Jang
- 👤 Sa Yoon Kang
- 👤 Heung Kyu Kwon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:39
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/01; H10W72/0198; H10D; H10D62/00; H10D62/10; H10D62/117; H10W42/00; H10W42/121; H10W72/20; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/012; H10W72/01221; H10W72/01223; H10W72/01225; H10W72/01251; H10W72/01255; H10W72/013; H10W72/01331; H10W72/072; H10W72/07251; H10W72/241; H10W72/242; H10W72/251; H10W72/252; H10W72/281; H10W72/283; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
116 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon; forming a patterned conductor layer directly on the passivation layer; forming an insulation layer on the patterned conductor layer; forming a plurality of external terminals of the semiconductor package; and sawing the wafer to separate the semiconductor integrated circuit chips, wherein the patterned conductor layer connects the chip pads to respective external terminals, and the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer.
Claim 2
Independent Claim
116 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon; forming a patterned conductor layer directly on the passivation layer; forming an insulation layer on the patterned conductor layer; forming a plurality of external terminals of the semiconductor package; and sawing the wafer to separate the semiconductor integrated circuit chips, wherein the patterned conductor layer connects the chip pads to respective external terminals, and the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer.
Claim 3
Dependent Claim
52 words
The method of claim 1 , wherein forming the external terminals comprises: placing solder balls at the openings in the insulation layer so that each solder ball sits on an associated opening; and heating the solder balls to reshape the solder balls and attach the solder balls to the patterned conductor layer.
Claim 4
Dependent Claim
59 words
The method of claim 1 , wherein forming the external terminals comprises: screen-printing solder paste using a mask having a plurality of mask openings, each of the mask openings corresponding to a respective one of the openings in the insulation layer; heating the solder paste to form solder bumps attached to bump pads formed in the patterned conductor layer.
Claim 5
Dependent Claim
21 words
The method of claim 1 , wherein forming the patterned conductor layer comprises screen-printing a conductive paste and curing the paste.
Claim 6
Dependent Claim
22 words
The method of claim 1 , wherein forming the patterned conductor layer comprises plating a metal layer and etching the metal layer.
Claim 7
Dependent Claim
27 words
The method of claim 1 , wherein the insulation layer contains a polymeric material that is selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.
Claim 8
Dependent Claim
21 words
The method of claim 1 , further comprising forming a chip protection layer on a back side of the semiconductor wafer.
Claim 9
Dependent Claim
17 words
The method of claim 7 , wherein the chip protection layer is formed by a spin-coating method.
Claim 10
Dependent Claim
25 words
The method of claim 1 , further comprising forming a chip edge protection layer along scribe lines on a top surface of the semiconductor wafer.
Claim 11
Dependent Claim
25 words
The method of claim 9 , wherein forming the chip edge protection layer comprises dispensing a liquid material on the scribe lines on the wafer.
Claim 12
Independent Claim
134 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon; forming a patterned conductor layer directly on the passivation layer; forming an insulation layer on the patterned conductor layer; forming a plurality of external terminals of the semiconductor package, wherein the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer, and the patterned conductor layer connects the chip pads to respective external terminals; forming a reinforcing layer on the insulation layer, wherein the external terminals are exposed through the reinforcing layer; and sawing the wafer to separate the semiconductor integrated circuit chips.
Claim 13
Independent Claim
134 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon; forming a patterned conductor layer directly on the passivation layer; forming an insulation layer on the patterned conductor layer; forming a plurality of external terminals of the semiconductor package, wherein the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer, and the patterned conductor layer connects the chip pads to respective external terminals; forming a reinforcing layer on the insulation layer, wherein the external terminals are exposed through the reinforcing layer; and sawing the wafer to separate the semiconductor integrated circuit chips.
Claim 14
Dependent Claim
15 words
The method of claim 11 , wherein the reinforcing layer is formed of a polymer.
Claim 15
Dependent Claim
24 words
The method of claim 12 , wherein forming the reinforcing layer comprises dispensing a liquid polymer for the reinforcing layer and curing the polymer.
Claim 16
Dependent Claim
22 words
The method of claim 11 , wherein the reinforcing layer is below a surface that connects the tips of the external terminals.
Claim 17
Dependent Claim
28 words
The method of claim 14 , wherein a perpendicular distance from the surface to a point where the reinforcing layer meets the external terminals is about 100 μm.
Claim 18
Independent Claim
172 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor integrated circuit chips having a plurality of chip pads and a passivation layer thereon; forming a lower insulation layer on the passivation layer of the semiconductor chip, the lower insulation layer having openings over the chip pads; forming a patterned conductor layer which connects to the chip pads through the openings in the lower insulation layer; forming an upper insulation layer on the patterned conductor layer, the upper insulation layer having openings which expose portions of the patterned conductor layer; forming a plurality of external terminals of the semiconductor package at the openings in the upper insulation layer, the external terminals connecting to the patterned conductor layer, wherein the patterned conductor layer interconnects each of the chip pads to respective external terminals; forming a reinforcing layer on the upper insulation layer; and sawing the wafer to separate the semiconductor integrated circuit chips.
Claim 19
Independent Claim
172 words
A method for manufacturing a semiconductor package, comprising: providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor integrated circuit chips having a plurality of chip pads and a passivation layer thereon; forming a lower insulation layer on the passivation layer of the semiconductor chip, the lower insulation layer having openings over the chip pads; forming a patterned conductor layer which connects to the chip pads through the openings in the lower insulation layer; forming an upper insulation layer on the patterned conductor layer, the upper insulation layer having openings which expose portions of the patterned conductor layer; forming a plurality of external terminals of the semiconductor package at the openings in the upper insulation layer, the external terminals connecting to the patterned conductor layer, wherein the patterned conductor layer interconnects each of the chip pads to respective external terminals; forming a reinforcing layer on the upper insulation layer; and sawing the wafer to separate the semiconductor integrated circuit chips.
Claim 20
Dependent Claim
29 words
The method of claim 16 , wherein the upper insulation layer contains a polymeric material which is one selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.
Claim 21
Dependent Claim
15 words
The method of claim 16 , wherein the lower insulation layer contains a polymeric material.
Claim 22
Dependent Claim
22 words
The method of claim 16 , wherein the polymeric material is selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.
Claim 23
Dependent Claim
17 words
The method of claim 16 , wherein the lower insulation layer is formed of an inorganic material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-13 | 2004-08-14 | 2005-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-13 | 2008-08-14 | 2009-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-13 | 2012-08-14 | 2013-02-13 | $7700.00 | Window Closed / Lapsed |