US6185324B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor failure analysis system
Assignee: Hitachi Ltd
•
Filing: 1995-01-31
•
Granted: 2001-02-06
•
Expires: 2015-01-31
Abstract
Abstract A semiconductor failure analysis system which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for examining relations between various types of inspection data obtained by inspection of the semiconductor and for examining relations between said inspection data and the failure information, a storage unit for storing information concerned with design of said semiconductor, an analysis unit for analyzing the failure information on the basis of output information output from the failure information collection unit, output information output from the inspection unit and design information stored in the storage unit, a display unit for displaying at least one of the result of analysis output from the analysis unit and the failure information, a failure cause estimation unit for estimating a cause of said failure information, and an unit for feeding the estimated cause of said failure information back to a process in which the failure has occurred.
Inventors
- 👤 Kazuko Ishihara
- 👤 Seiji Ishikawa
- 👤 Masao Sakata
- 👤 Isao Miyazaki
- 👤 Yoshiyuki Miyamoto
- 👤 Jun Nakazato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:17
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; G; G01; G01N; G01N21/00; G01N21/84; G01N21/88; G01N21/95; G01N21/956
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
225 words
A semiconductor failure analysis system comprising: means for detecting electrical fail bits in a semiconductor chip or in a wafer; means for memorizing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; means for dividing a first area of the semiconductor chip or the wafer into a plurality of second areas; means for specifying a third area covering only a portion of an entire surface area of one of the second areas in which said electrical fail bits are distributed; means for dividing the specified third area into a number of shapes in accordance with the kinds of predetermined shaped patterns; means for discriminating a kind of a predetermined shaped pattern from a thus divided shape of said specified third area; means for performing data compression of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to the kind of said predetermined shaped pattern thus discriminated, means for abstracting a representative shaped pattern of the third area from the discriminated shaped patterns; means for displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture; and means for displaying the electrical fail bits distribution of the third area.
Claim 2
Dependent Claim
225 words
A semiconductor failure analysis system comprising: means for detecting electrical fail bits in a semiconductor chip or in a wafer; means for memorizing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; means for dividing a first area of the semiconductor chip or the wafer into a plurality of second areas; means for specifying a third area covering only a portion of an entire surface area of one of the second areas in which said electrical fail bits are distributed; means for dividing the specified third area into a number of shapes in accordance with the kinds of predetermined shaped patterns; means for discriminating a kind of a predetermined shaped pattern from a thus divided shape of said specified third area; means for performing data compression of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to the kind of said predetermined shaped pattern thus discriminated, means for abstracting a representative shaped pattern of the third area from the discriminated shaped patterns; means for displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture; and means for displaying the electrical fail bits distribution of the third area.
Claim 3
Dependent Claim
38 words
A system according to claim 1 , wherein the pattern shapes of said divided area include at least two shapes taken from the group of shapes consisting of a tetragonal shape, a line shape, and a dot shape.
Claim 4
Dependent Claim
58 words
A system according to claim 2 , wherein in a case where the pattern shapes include the line shape, said data compressing means performs data compression thereof by using an address of a head fail bit of that line shape and a number of fail bits indicative of the total number of fail bits of that line shape.
Claim 5
Dependent Claim
41 words
A system according to claim 2 , wherein in a case where the pattern shapes include a tetragonal shape, said data compressing means performs data compression thereof by using addresses of one pair of diagonally disposed apexes of said tetragonal shape.
Claim 6
Dependent Claim
27 words
A system according to claim 1 , wherein said fail bits are detected as bits which do not satisfy a predetermined electrical property by a probe tester.
Claim 7
Dependent Claim
269 words
A semiconductor failure analysis system comprising: a probe tester for detecting electrical fail bits on a wafer or on a chip; and a data processing apparatus connected to said probe tester, wherein said data processing apparatus includes (i) a memory for storing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; and (ii) a central processing unit (CPU) for analyzing a distribution of the electrical fail bits detected by said probe tester on said wafer, dividing a first area of the semiconductor chip or the wafer into a plurality of second areas, specifying a third area covering only a portion of an entire surface area of one of the second areas, in which said electrical fail bits are distributed, dividing a defective part of the specified third area of said wafer or chip formed by electrical fail bits thus analyzed into a number of different standard pattern shapes in accordance with the kinds of predetermined shaped patterns, discriminating a predetermined shaped pattern from a thus divided shape of said defective part, performing data compression of data of electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to said thus discriminated predetermined shaped pattern stored in said memory, abstracting a representative shaped pattern of the third area from the discriminated shaped patterns, displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture, and displaying the electrical fail bits distribution of the third area.
Claim 8
Dependent Claim
269 words
A semiconductor failure analysis system comprising: a probe tester for detecting electrical fail bits on a wafer or on a chip; and a data processing apparatus connected to said probe tester, wherein said data processing apparatus includes (i) a memory for storing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; and (ii) a central processing unit (CPU) for analyzing a distribution of the electrical fail bits detected by said probe tester on said wafer, dividing a first area of the semiconductor chip or the wafer into a plurality of second areas, specifying a third area covering only a portion of an entire surface area of one of the second areas, in which said electrical fail bits are distributed, dividing a defective part of the specified third area of said wafer or chip formed by electrical fail bits thus analyzed into a number of different standard pattern shapes in accordance with the kinds of predetermined shaped patterns, discriminating a predetermined shaped pattern from a thus divided shape of said defective part, performing data compression of data of electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to said thus discriminated predetermined shaped pattern stored in said memory, abstracting a representative shaped pattern of the third area from the discriminated shaped patterns, displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture, and displaying the electrical fail bits distribution of the third area.
Claim 9
Dependent Claim
36 words
A semiconductor failure analysis system according to claim 6 , wherein said pattern shapes include at least two taken from the group of shapes consisting of a tetragonal shape, a line shape, and a dot shape.
Claim 10
Dependent Claim
55 words
A semiconductor failure analysis system according to claim 7 , wherein in a case where the pattern shapes include the line shape, data compression thereof is performed by using an address of a head fail bit and a number of fail bits indicative of the total number of fail bits corresponding to that line shape.
Claim 11
Dependent Claim
41 words
A semiconductor failure analysis system according to claim 7 , wherein in a case where the pattern shapes include the tetragonal shape, data compression thereof is performed by using addresses of one pair of diagonally disposed apexes of said tetragonal shape.
Claim 12
Dependent Claim
236 words
A data processing apparatus comprising: a memory storing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; and a central processing unit (CPU) for analyzing a distribution of electrical fail bits on a wafer or on a chip detected by a probe tester, dividing a first area of the semiconductor chip or the wafer into a plurality of second areas, specifying a third area covering only a portion of an entire surface area of one of the second areas, in which said electrical fail bits are distributed; dividing a defective part of the specified third area of said wafer formed by electrical fail bits thus analyzed into a number of different standard pattern shapes in accordance with the kinds of predetermined shaped patterns, discriminating a predetermined shaped pattern from a thus divided shape of said defective part, performing data compression of data of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to said thus discriminated predetermined shaped pattern stored in said memory, abstracting a representative shaped pattern of the third area from the discriminated shaped patterns, displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture, and displaying the electrical fail bits distribution of the third area.
Claim 13
Dependent Claim
236 words
A data processing apparatus comprising: a memory storing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; and a central processing unit (CPU) for analyzing a distribution of electrical fail bits on a wafer or on a chip detected by a probe tester, dividing a first area of the semiconductor chip or the wafer into a plurality of second areas, specifying a third area covering only a portion of an entire surface area of one of the second areas, in which said electrical fail bits are distributed; dividing a defective part of the specified third area of said wafer formed by electrical fail bits thus analyzed into a number of different standard pattern shapes in accordance with the kinds of predetermined shaped patterns, discriminating a predetermined shaped pattern from a thus divided shape of said defective part, performing data compression of data of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to said thus discriminated predetermined shaped pattern stored in said memory, abstracting a representative shaped pattern of the third area from the discriminated shaped patterns, displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture, and displaying the electrical fail bits distribution of the third area.
Claim 14
Dependent Claim
40 words
A data processing apparatus according to claim 10 , wherein the pattern shapes of said area divided include at least two shapes taken from the group of shapes consisting of a tetragonal shape, a line shape, and a dot shape.
Claim 15
Dependent Claim
53 words
A data processing apparatus according to claim 11 , wherein in a case where the pattern shapes include the line shape, data compression thereof is performed by using an address of a head fail bit and a number of fail bits indicative of the total number of fail bits in that line shape.
Claim 16
Dependent Claim
40 words
A data processing apparatus according to claim 11 , wherein in a case where the pattern shapes include the tetragonal shape, data compression thereof is performed by using addresses of a pair of diagonally disposed apexes of said tetragonal shape.
Claim 17
Dependent Claim
211 words
A semiconductor failure analysis method comprising the steps of: detecting electrical fail bits in a semiconductor chip or in a wafer; memorizing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; dividing a first area of the semiconductor chip or the wafer into a plurality of second areas; specifying a third area covering only a portion of an entire surface area of one of the second areas in which said electrical fail bits are distributed; dividing said specified third area into a number of different standard pattern shapes in accordance with the kinds of predetermined shape patterns; discriminating a kind of a predetermined shaped pattern from a thus divided shape of said specified third area; performing data compression of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to the kind of said predetermined shaped pattern thus discriminated; abstracting a representative shaped pattern of the third area from the discriminated shaped patterns; displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture; and displaying the electrical fail bits distribution of the third area.
Claim 18
Dependent Claim
211 words
A semiconductor failure analysis method comprising the steps of: detecting electrical fail bits in a semiconductor chip or in a wafer; memorizing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns; dividing a first area of the semiconductor chip or the wafer into a plurality of second areas; specifying a third area covering only a portion of an entire surface area of one of the second areas in which said electrical fail bits are distributed; dividing said specified third area into a number of different standard pattern shapes in accordance with the kinds of predetermined shape patterns; discriminating a kind of a predetermined shaped pattern from a thus divided shape of said specified third area; performing data compression of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to the kind of said predetermined shaped pattern thus discriminated; abstracting a representative shaped pattern of the third area from the discriminated shaped patterns; displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture; and displaying the electrical fail bits distribution of the third area.
Claim 19
Dependent Claim
38 words
A method according to claim 14 , wherein the pattern shapes of said divided area include at least two shapes taken from the group of shapes consisting of a tetragonal shape, a line shape, and a dot shape.
Claim 20
Dependent Claim
55 words
A method according to claim 15 , wherein in a case where the pattern shapes include the line shape, data compression thereof is performed by using an address of a head fail bit of that line shape and a number of fail bits indicative of the total number of fail bits of that line shape.
Claim 21
Dependent Claim
38 words
A method according to claim 15 , wherein in a case where the pattern shapes include the tetragonal shape, data compression thereof is performed by using addresses of a pair of diagonally disposed apexes of said tetragonal shape.
Claim 22
Dependent Claim
27 words
A system according to claim 14 , wherein said fail bits are detected as bits which do not satisfy a predetermined electrical property by a probe tester.
References Cited (Backward Citations)
US3873972A
Cited
US4189711A
Cited
US4365318A
Cited
US4449818A
Cited
JPS59228726A
Cited
US4719357A
Cited
US4659220A
Cited
US4928313A
Cited
US4969198A
Cited
US4908871A
Cited
US4783841A
Cited
US4965515A
Cited
US5153444A
Cited
US5228097A
Cited
US5216726A
Cited
US5109438A
Cited
US5070532A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |