US6184547B1
Expired / Lapsed
US
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Field effect transistor and method of fabricating the same
Assignee: NEC Corp
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Filing: 1999-09-15
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Granted: 2001-02-06
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Expires: 2019-09-15
Abstract
Abstract There is provided a field effect transistor including a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, a gate base layer formed on the recess and composed of one of an InP layer and a plurality of layers including an InP layer, and a gate electrode formed on the gate base layer. The InP layer may be replaced with an InGaP layer, an Al X Ga 1−X As (0≦X≦1) layer, an In X Ga 1−X As (0≦X≦1) layer, or an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer. The above-mentioned field effect transistor prevents thermal instability thereof caused by impurities such as fluorine entering a donor layer to thereby inactivate donor. As a result, there is presented a highly reliable compound field effect transistor.
Inventors
- 👤 Kazuhiko Onda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
111 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer.
Claim 2
Dependent Claim
111 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer.
Claim 3
Dependent Claim
30 words
The field effect transistor as set forth in claim 1 , further comprising an InAlAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 4
Dependent Claim
30 words
The field effect transistor as set forth in claim 1 , further comprising an AlGaAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 5
Dependent Claim
20 words
The field effect transistor as set forth in claim 1 , wherein said semi-insulating semiconductor substrate is composed of InP.
Claim 6
Dependent Claim
41 words
The field effect transistor as set forth in claim 1 , wherein a portion of said gate base layer extends beyond a periphery of said recess and is directly on a top surface of said top layer adjacent to said recess.
Claim 7
Dependent Claim
45 words
The field effect transistor as set forth in claim 5 , further comprising source and drain electrodes that are directly on the top surface of said top layer and separated from said portion of said gate base layer that is directly on the top surface.
Claim 8
Dependent Claim
146 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising a plurality of layers including an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer, wherein a portion of said gate base layer extends beyond a periphery of said recess and is directly on a top surface of said top layer adjacent to said recess.
Claim 9
Dependent Claim
146 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising a plurality of layers including an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer, wherein a portion of said gate base layer extends beyond a periphery of said recess and is directly on a top surface of said top layer adjacent to said recess.
Claim 10
Dependent Claim
45 words
The field effect transistor as set forth in claim 7 , further comprising source and drain electrodes that are directly on the top surface of said top layer and separated from said portion of said gate base layer that is directly on the top surface.
Claim 11
Dependent Claim
30 words
The field effect transistor as set forth in claim 7 , further comprising an InAlAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 12
Dependent Claim
30 words
The field effect transistor as set forth in claim 7 , further comprising an AlGaAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 13
Dependent Claim
20 words
The field effect transistor as set forth in claim 7 , wherein said semi-insulating semiconductor substrate is composed of InP.
Claim 14
Dependent Claim
118 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising one of a plurality of layers including an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer.
Claim 15
Dependent Claim
118 words
A field effect transistor comprising: a semi-insulating semiconductor substrate; an epitaxial, layered structure on said substrate and having a recess therein at a region in which a gate is to be formed, said layered structure comprising an impurity doped top layer and an undoped layer directly beneath said top layer, said recess extending completely through said top layer and into, but not through, said undoped layer; a gate base layer formed directly on portions of said top layer and said undoped layer exposed in said recess, said gate base layer comprising one of a plurality of layers including an In X Al 1−X As (0≦X<0.4 or 0.6<X≦1) layer; and a gate electrode formed on said gate base layer.
Claim 16
Dependent Claim
30 words
The field effect transistor as set forth in claim 12 , further comprising an InAlAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 17
Dependent Claim
30 words
The field effect transistor as set forth in claim 12 , further comprising an AlGaAs layer containing no impurities therein, formed between said gate base layer and said gate electrode.
Claim 18
Dependent Claim
20 words
The field effect transistor as set forth in claim 12 , wherein said semi-insulating semiconductor substrate is composed of InP.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |