Patent US6184085B1 successfully refreshed from Google Patents.
US6184085B1
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Methods of forming nonvolatile memory devices using improved masking techniques
Assignee: Samsung Electronics Co Ltd
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Filing: 1999-06-10
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Granted: 2001-02-06
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Expires: 2019-06-10
Abstract
Abstract Methods of forming nonvolatile memory devices include the steps of forming a plurality of field oxide isolation regions on a semiconductor substrate. A thermal oxidation step may then be performed to define first gate insulating layers on active regions within the substrate. A blanket layer of polysilicon is then deposited as a first electrically conductive layer. Next, a blanket layer of an electrically insulating layer, which may comprise an oxide-nitride-oxide (ONO) composite insulating layer, is deposited. A blanket photoresist layer is then deposited on the electrically insulating layer. Conventional photolithography steps may then be performed to convert the blanket photoresist layer into a photoresist pattern on a memory cell array portion of the substrate. A dry etching step is then performed to define a floating gate electrode having an ONO electrically insulating cap thereon, on the memory cell array portion of the substrate. A wet etching step is then performed to remove the first gate insulating layer from the peripheral circuit portion of the substrate. This wet etching step is performed using the same mask (i.e., photoresist pattern) that was used during the dry etching step. Because this etching step causes portions of the floating gate electrodes to be undercut, a thermal oxidation step is then performed to grow sidewall insulating spacers on the sidewalls and undercut portions of the floating gate electrodes. Based on this thermal oxidation step, the floating gate electrodes become encapsulated by electrically insulating material.
Inventors
- 👤 Jae-Ik Jeong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:30
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/40; H10B41/30; H10B41/42; H10B41/43; H10B41/48
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
138 words
A method of forming a memory cell having a floating gate therein, comprising the steps of: forming a first electrically insulating layer on a surface of a semiconductor substrate; forming a first conductive layer on the first electrically insulating layer, opposite the surface; forming a second electrically insulating layer on the first conductive layer, opposite the first electrically insulating layer; patterning the second electrically insulating and the first conductive layer to define a floating gate electrode having exposed sidewalls; etching the first electrically insulating layer to define a recess therein that undercuts a portion of the floating gate electrode extending adjacent the exposed sidewalls; oxidizing the exposed sidewalls and the undercut portion of the floating gate electrode to define sidewall insulating spacers; and forming a control electrode on the second electrically insulating layer, opposite the floating gate electrode.
Claim 2
Independent Claim
138 words
A method of forming a memory cell having a floating gate therein, comprising the steps of: forming a first electrically insulating layer on a surface of a semiconductor substrate; forming a first conductive layer on the first electrically insulating layer, opposite the surface; forming a second electrically insulating layer on the first conductive layer, opposite the first electrically insulating layer; patterning the second electrically insulating and the first conductive layer to define a floating gate electrode having exposed sidewalls; etching the first electrically insulating layer to define a recess therein that undercuts a portion of the floating gate electrode extending adjacent the exposed sidewalls; oxidizing the exposed sidewalls and the undercut portion of the floating gate electrode to define sidewall insulating spacers; and forming a control electrode on the second electrically insulating layer, opposite the floating gate electrode.
Claim 3
Dependent Claim
71 words
The method of claim 1 , wherein the first electrically insulating layer comprises a field oxide insulating layer; wherein the field oxide insulating layer has openings therein which expose active portions of the semiconductor substrate; and wherein said step of forming a first conductive layer on the first electrically insulating layer is preceded by the step of forming a plurality of gate oxide insulating layers on active portions of the substrate.
Claim 4
Dependent Claim
77 words
The method of claim 2 , wherein the floating gate electrode contacts one of the gate oxide insulating layers; wherein the substrate includes a memory cell array region and a peripheral circuit region therein; and wherein said step of etching the first electrically insulating layer comprises simultaneously etching a portion of the field oxide insulating layer extending opposite the memory cell array region and another of the gate oxide insulating layers extending opposite the peripheral circuit region.
Claim 5
Dependent Claim
18 words
The method of claim 3 , wherein the second electrically insulating layer comprises an oxide-nitride-oxide composite insulating layer.
Claim 6
Dependent Claim
22 words
The method of claim 4 , wherein the first conductive layer comprises polysilicon; and wherein the control electrode comprises a polysilicide material.
Claim 7
Dependent Claim
18 words
The method of claim 1 , wherein the second electrically insulating layer comprises an oxide-nitride-oxide composite insulating layer.
Claim 8
Dependent Claim
22 words
The method of claim 6 , wherein the first conductive layer comprises polysilicon; and wherein the control electrode comprises a polysilicide material.
Claim 9
Independent Claim
201 words
A method of forming a nonvolatile memory device, comprising the steps of: forming a field oxide isolation region in a portion of a semiconductor substrate containing memory cell array and peripheral circuit regions therein; forming a first gate oxide insulating layer on active portions of the memory cell array region and active portions of the peripheral circuit region; forming a first conductive layer on the first gate oxide insulating layer and on the field oxide isolation region; forming a second electrically insulating layer on the first conductive layer; patterning the second electrically insulating and the first conductive layer to define a floating gate electrode on the memory cell array region; simultaneously etching a portion of the field oxide isolation region extending opposite the memory cell array region and a portion of the first gate oxide insulating layer extending opposite the peripheral circuit region to expose the active portion of the peripheral circuit region and define a recess in the field oxide isolation region which undercuts the floating gate electrode; oxidizing sidewalls and an undercut portion of the floating gate electrode to define sidewall insulating spacers; and forming a control electrode on the second electrically insulating layer, opposite the floating gate electrode.
Claim 10
Independent Claim
201 words
A method of forming a nonvolatile memory device, comprising the steps of: forming a field oxide isolation region in a portion of a semiconductor substrate containing memory cell array and peripheral circuit regions therein; forming a first gate oxide insulating layer on active portions of the memory cell array region and active portions of the peripheral circuit region; forming a first conductive layer on the first gate oxide insulating layer and on the field oxide isolation region; forming a second electrically insulating layer on the first conductive layer; patterning the second electrically insulating and the first conductive layer to define a floating gate electrode on the memory cell array region; simultaneously etching a portion of the field oxide isolation region extending opposite the memory cell array region and a portion of the first gate oxide insulating layer extending opposite the peripheral circuit region to expose the active portion of the peripheral circuit region and define a recess in the field oxide isolation region which undercuts the floating gate electrode; oxidizing sidewalls and an undercut portion of the floating gate electrode to define sidewall insulating spacers; and forming a control electrode on the second electrically insulating layer, opposite the floating gate electrode.
Claim 11
Dependent Claim
18 words
The method of claim 8 , wherein the second electrically insulating layer comprises an oxide-nitride-oxide composite insulating layer.
Claim 12
Dependent Claim
22 words
The method of claim 9 , wherein the first conductive layer comprises polysilicon; and wherein the control electrode comprises a polysilicide material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |