Patent US6184048B1 successfully refreshed from Google Patents.
US6184048B1
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US
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Testing method and apparatus assuring semiconductor device quality and reliability
Assignee: Texas Instruments Inc
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Filing: 1999-11-03
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Granted: 2001-02-06
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Expires: 2019-11-03
Abstract
Abstract A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising first, electrically testing the devices outside their specified operating voltage range, yet within the capabilities of the structures produced by the process steps, thereby generating raw electrical test data; second, comparing the test data to values expected from the design of the devices, thereby providing non-electrical characterization of the devices to verify compositional and structural features; and third, correlating the features with the documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices. After eliminating the outlier devices, the accepted devices do no longer have to undergo the traditional burn-in process.
Inventors
- 👤 Joseph Ramon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:21
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
97 words
A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising: electrically testing said devices outside their specified operating voltage range, yet within the capabilities of the structures produced by said process steps, thereby generating raw electrical test data; comparing said test data to values expected from the design of said devices, thereby providing non-electrical characterization of said devices to verify compositional and structural features; and correlating said features with said documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices.
Claim 2
Independent Claim
97 words
A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising: electrically testing said devices outside their specified operating voltage range, yet within the capabilities of the structures produced by said process steps, thereby generating raw electrical test data; comparing said test data to values expected from the design of said devices, thereby providing non-electrical characterization of said devices to verify compositional and structural features; and correlating said features with said documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices.
Claim 3
Dependent Claim
50 words
The method according to claim 1 wherein said testing comprises: inputting test voltages higher than specification at input terminals selected on circuit design; measuring quiescent leakage current; and correlating said leakage current with pre-defined limits, thereby finding devices with leakage current higher than the pre-defined limits as reason for rejection.
Claim 4
Dependent Claim
37 words
The method according to claim 2 further comprising the steps of stressing said devices and repeating the measurement of said leakage current, thereby detecting any difference between first and second leakage, causing said devices to be rejected.
Claim 5
Dependent Claim
44 words
The method according to claim 2 further comprising the step of repeating the measurement of said leakage current at different logic state of said devices, thereby detecting any difference between first and second leakage, causing said devices to undergo distribution testing and potential rejection.
Claim 6
Dependent Claim
50 words
The method according to claim 1 wherein said testing comprises: inputting test voltages lower than specification at input terminals selected on circuit design; measuring quiescent leakage current; and correlating said leakage current with pre-defined limits, thereby finding devices with leakage current higher than the pre-defined limits as reason for rejection.
Claim 7
Dependent Claim
49 words
The method according to claim 1 wherein said testing comprises: inputting test voltages in a voltage range at least as great as the specified input voltage range at input terminals selected on circuit design; measuring output voltages at selected output terminals to determine state of said circuit at output.
Claim 8
Dependent Claim
25 words
The method according to claim 6 wherein said voltage range is determined by said capabilities of said process steps used for fabricating said semiconductor devices.
Claim 9
Dependent Claim
22 words
The method according to claim 6 wherein said voltage range includes higher as well as lower voltages than defined by device specification.
Claim 10
Dependent Claim
65 words
The method according to claim 1 wherein said testing comprises: inputting a high test voltage, the high test voltage near the device's specified maximum input voltage and measuring quiescent leakage current; inputting a low test voltage, the low test voltage near the device's specified minimum input voltage and measuring quiescent leakage current; and interpolating the data for determining a linear relation as reason for rejection.
Claim 11
Dependent Claim
39 words
The method according to claim 1 wherein said testing comprises: measuring input leakage current; correlating said leakage current with pre-defined limits set lower than specification, thereby finding devices with leakage current higher than pre-defined limits as reason for rejection.
Claim 12
Dependent Claim
35 words
The method according to claim 1 wherein said testing comprises: measuring electrical parameters related to process parameters having low Cpk; correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.
Claim 13
Dependent Claim
15 words
The method according to claim 1 wherein said electrical testing is performed at ambient temperature.
Claim 14
Dependent Claim
24 words
The method according to claim 1 wherein said testing eliminates the need for burn-in of all said circuits which pass said testing and correlating.
Claim 15
Dependent Claim
18 words
The method according to claim 1 wherein said testing results in devices having a voltage margin of ±25%.
Claim 16
Dependent Claim
19 words
The method according to claim 1 wherein said electrical testing excludes functional tests at the device's rated operating speed.
Claim 17
Dependent Claim
16 words
The method according to claim 1 wherein said electrical testing excludes functional tests at 400 megahertz.
Claim 18
Dependent Claim
37 words
The method according to claim 1 wherein said testing comprises: measuring electrical parameters related to process parameters having Cpk below about 1.5; correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.
Claim 19
Dependent Claim
36 words
The method according to claim 1 wherein said testing comprises: measuring electrical parameters related to process parameters having Cpk below 2; correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.
References Cited (Backward Citations)
US5497381A
Cited
US6013533A
Cited
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