US6182203B1
Expired / Lapsed
US
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Microprocessor
Assignee: Texas Instruments Inc
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Filing: 1998-01-23
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Granted: 2001-01-30
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Expires: 2018-01-23
Abstract
Abstract A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.
Inventors
- 👤 Laurence R. Simar, Jr.
- 👤 Richard H. Scales
- 👤 Natarajan Seshan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/3891; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/7857; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30072; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/3012; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/34; G06F9/355; G06F9/3552; G06F9/3824; G06F9/3826; G06F9/3828; G06F9/3836; G06F9/3853
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
183 words
A microprocessor comprising: fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions; a first set of functional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types; a second set of functional units connected to receive instructions from the fetch circuitry; wherein the second set of functional units is operable to execute the first plurality of instruction types; dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel; and wherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.
Claim 2
Dependent Claim
183 words
A microprocessor comprising: fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions; a first set of functional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types; a second set of functional units connected to receive instructions from the fetch circuitry; wherein the second set of functional units is operable to execute the first plurality of instruction types; dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel; and wherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.
Claim 3
Dependent Claim
17 words
The microprocessor of claim 1 , wherein each of said sets of functional units includes a multiplier.
Claim 4
Dependent Claim
25 words
The microprocessor of claim 1 , wherein each of said sets of functional units includes a logic unit capable of selected logic and arithmetic operations.
Claim 5
Dependent Claim
26 words
The microprocessor of claim 1 , wherein each of said sets of functional units includes a logic unit capable of selected logic, arithmetic and shift operations.
Claim 6
Dependent Claim
25 words
The microprocessor of claim 1 , wherein each of said sets of functional units includes a logic unit capable of selected arithmetic and data operations.
Claim 7
Dependent Claim
45 words
The microprocessor of claim 1 , wherein the dispatch circuitry is further operable to simultaneously dispatch a first instruction of a first type to the first set of functional units, and a second instruction of the first type to the second set of functional units.
Claim 8
Dependent Claim
30 words
The microprocessor of claim 6 , wherein the first set of functional units comprises a first register file and the second set of functional units comprises a second register file.
Claim 9
Dependent Claim
36 words
The microprocessor of claim 7 , wherein the first set of functional units is interconnected to access the second register file and the second set of functional units is interconnected to access the first register file.
Claim 10
Dependent Claim
190 words
A digital system comprising a microprocessor, wherein the microprocessor comprises: fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions; a first set of fimctional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types; a second set of functional units connected to receive instructions from the fetch circuitry; wherein the second set of functional units is operable to execute the first plurality of instruction types; dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel, and wherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.
Claim 11
Dependent Claim
190 words
A digital system comprising a microprocessor, wherein the microprocessor comprises: fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions; a first set of fimctional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types; a second set of functional units connected to receive instructions from the fetch circuitry; wherein the second set of functional units is operable to execute the first plurality of instruction types; dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel, and wherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.
Claim 12
Dependent Claim
45 words
The system of claim 9 , wherein the dispatch circuitry is further operable to simultaneously dispatch a first instruction of a first type to the first set of functional units, and a second instruction of the first type to the second set of functional units.
Claim 13
Dependent Claim
25 words
The system of claim 10 being a modem, further comprising an analog-to-digital or digital-to-analog converter interfaced to the microprocessor for connection to a telephone line.
Claim 14
Dependent Claim
56 words
The system of claim 10 being an electronic automotive control system responsive to instructions defined by electrical bits, said electronic automotive control system further comprising an interface coupled to said microprocessor for supplying selected bits to cause a change in at least one of a braking system, a suspension system, or an engine of an automobile.
Claim 15
Dependent Claim
58 words
The system of claim 10 being a process control system, further comprising: sensors connected to said microprocessor responsive to a state of a process, process control elements responsive to electronic directions operable to change at least one parameter of said process, and an interface connected to said microprocessor for supplying selected electronic directions to said process control elements.
Claim 16
Independent Claim
224 words
A method of operating a digital system having a microprocessor, the method comprising the steps of: fetching a sequence of execution packets for execution by the microprocessor, wherein each execution packet contains up to N instructions that are executed in parallel by the microprocessor; dispatching all instructions of a first execution packet for parallel execution on plural sets of functional units in the microprocessor, wherein the plural sets of finctional units are virtually identical, wherein each instruction of each execution packet is selectively dispatched to either a first set of functional units or to a second set of functional units in response to a bit in each instruction; executing all instructions of the first execution packet in parallel on the plural sets of functional units; and repeating the steps of dispatching and executing for each execution packet of the sequence of execution packets, such that for each execution packet instructions of the same type can be dispatched to any and all of the plural sets of functional units, such that a first instruction of a first type from a given first execution packet is executed on the first set of the plural sets of finctional units while a second instruction of the first type from the given execution packet is executed in parallel on the second set of the plural sets of functional units.
Claim 17
Independent Claim
224 words
A method of operating a digital system having a microprocessor, the method comprising the steps of: fetching a sequence of execution packets for execution by the microprocessor, wherein each execution packet contains up to N instructions that are executed in parallel by the microprocessor; dispatching all instructions of a first execution packet for parallel execution on plural sets of functional units in the microprocessor, wherein the plural sets of finctional units are virtually identical, wherein each instruction of each execution packet is selectively dispatched to either a first set of functional units or to a second set of functional units in response to a bit in each instruction; executing all instructions of the first execution packet in parallel on the plural sets of functional units; and repeating the steps of dispatching and executing for each execution packet of the sequence of execution packets, such that for each execution packet instructions of the same type can be dispatched to any and all of the plural sets of functional units, such that a first instruction of a first type from a given first execution packet is executed on the first set of the plural sets of finctional units while a second instruction of the first type from the given execution packet is executed in parallel on the second set of the plural sets of functional units.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |