US6175898B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for prefetching data using a micro-TLB
Assignee: Oracle America Inc
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Filing: 1997-06-23
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Granted: 2001-01-16
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Expires: 2017-06-23
Abstract
Abstract A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline ( 324 ) by searching a data cache ( 310 ) and a prefetch cache ( 320 ). A large data TLB ( 330 ) provides memory for storing address translations for the first pipeline ( 324 ) A second pipeline ( 328 ) executes memory instructions by accessing the prefetch cache ( 320 ). A second micro-TLB ( 340 ) is associated with the second pipeline ( 328 ). It is loaded in anticipation of data that will be referenced by the second pipeline ( 328 ). A history file ( 360 ) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic ( 370 ) determines when to prefetch data, and steering logic ( 380 ) routes certain instructions to the second pipeline ( 328 ) to increase system performance.
Inventors
- 👤 Sultan Ahmed
- 👤 Joseph Chamdani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/10; G06F12/1027; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30047; G06F9/34; G06F9/345; G06F9/3455; G06F9/38; G06F9/3824; G06F9/383; G06F9/3832; G06F2212/00; G06F2212/60; G06F2212/6026; G06F2212/68; G06F2212/681
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
111 words
A method of operating a data cache system comprising: executing a first memory instruction in a first execution pipeline; translating a virtual address of an operand referenced by the first memory instruction to a physical address producing an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer; selectively storing data in a second data cache in anticipation of the data being referenced by a second memory instruction; and executing the second memory instruction in a second execution pipeline by retrieving the address translation from the second translation lookaside buffer.
Claim 2
Independent Claim
111 words
A method of operating a data cache system comprising: executing a first memory instruction in a first execution pipeline; translating a virtual address of an operand referenced by the first memory instruction to a physical address producing an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer; selectively storing data in a second data cache in anticipation of the data being referenced by a second memory instruction; and executing the second memory instruction in a second execution pipeline by retrieving the address translation from the second translation lookaside buffer.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein the second memory instruction is a second iteration of the first memory instruction.
Claim 4
Dependent Claim
18 words
The method of claim 1 further comprising storing information about the first memory instruction in a history file.
Claim 5
Dependent Claim
26 words
The method of claim 3 wherein the address translation is selectively stored in the second translation lookaside buffer based on the information in the history file.
Claim 6
Dependent Claim
25 words
The method of claim 3 , wherein the data is selectively stored in the second data cache based upon the information in the history file.
Claim 7
Dependent Claim
29 words
The method of claim 1 wherein the data is selectively stored in the second data cache based upon the occurrence of a hit to the second translation lookaside buffer.
Claim 8
Dependent Claim
28 words
The method of claim 1 wherein the data is selectively stored in the second data cache based upon the occurrence of a hit to the second data cache.
Claim 9
Dependent Claim
16 words
The method of claim 1 wherein the second memory instruction is a floating point load command.
Claim 10
Dependent Claim
35 words
The method of claim 1 wherein the first execution pipeline searches for address translations in the first translation lookaside buffer and the second execution pipeline searches for address translation in the second translation lookaside buffer.
Claim 11
Dependent Claim
22 words
The method of claim 9 wherein the first execution pipeline does not search for address translations in the second translation lookaside buffer.
Claim 12
Dependent Claim
22 words
The method of claim 10 wherein the second execution pipeline does not search for address translations in the first translation lookaside buffer.
Claim 13
Independent Claim
169 words
A method of operating a data cache system comprising: executing a first memory instruction in a first execution pipeline; storing information about the first memory instruction in a history file; translating a virtual address of an operand referenced by the first memory instruction to a physical address to obtain an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer based on the information in the history file; selectively storing data in a prefetch cache in anticipation of the data being referenced by a second memory instruction based upon whether the first instruction caused a hit to at least one of the set that includes the prefetch cache, the second translation lookaside buffer and the history file; and selectively executing a second memory instruction in a second execution pipeline based upon the information in the history file by retrieving the address translation from the second translation lookaside buffer.
Claim 14
Independent Claim
169 words
A method of operating a data cache system comprising: executing a first memory instruction in a first execution pipeline; storing information about the first memory instruction in a history file; translating a virtual address of an operand referenced by the first memory instruction to a physical address to obtain an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer based on the information in the history file; selectively storing data in a prefetch cache in anticipation of the data being referenced by a second memory instruction based upon whether the first instruction caused a hit to at least one of the set that includes the prefetch cache, the second translation lookaside buffer and the history file; and selectively executing a second memory instruction in a second execution pipeline based upon the information in the history file by retrieving the address translation from the second translation lookaside buffer.
Claim 15
Dependent Claim
16 words
The method of claim 12 wherein the second memory instruction is a floating point load instruction.
Claim 16
Independent Claim
126 words
A method of operating a digital system comprising: issuing a first memory instructions from a processor; executing the first memory instruction in a first execution pipeline; translating a virtual address of an operand referenced by the first memory instruction to a physical address producing an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer; selectively storing data in a second data cache in anticipation of the data being referenced by a second memory instruction; issuing a second memory instruction from the processor; and executing the second memory instruction in a second execution pipeline by retrieving the address translation from the second translation lookaside buffer.
Claim 17
Independent Claim
126 words
A method of operating a digital system comprising: issuing a first memory instructions from a processor; executing the first memory instruction in a first execution pipeline; translating a virtual address of an operand referenced by the first memory instruction to a physical address producing an address translation; storing the address translation in a first translation lookaside buffer; storing the operand in a first data cache; selectively storing the address translation in a second translation lookaside buffer; selectively storing data in a second data cache in anticipation of the data being referenced by a second memory instruction; issuing a second memory instruction from the processor; and executing the second memory instruction in a second execution pipeline by retrieving the address translation from the second translation lookaside buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-16 | 2004-07-17 | 2005-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-16 | 2008-07-17 | 2009-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-16 | 2012-07-17 | 2013-01-16 | $7700.00 | Window Closed / Lapsed |