Shadow translation look-aside buffer and method of operation

Claim 2

For use in a processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache, a circuit for increasing a translation speed of said primary TLB, comprising: a shadow TLB, located proximate said cache, that contains a copy of physical addresses stored in said primary TLB, said physical addresses retrievable from said shadow TLB thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 3

The circuit as recited in claim 1 wherein said cache includes a tag array having multiple ones of said shadow TLB interleaved therein.

Claim 4

The circuit as recited in claim 2 wherein said cache is divided into separate, physically-addressable sectors and said tag array further has tag registers corresponding to each of said sectors.

Claim 5

The circuit as recited in claim 2 wherein said tag array further has at least one tag register and comparison circuitry that compares said multiple ones of said shadow TLB with said at least one tag register.

Claim 6

For use in a processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache, a circuit for increasing a translation speed of said primary TLB, comprising: shadow TLB means, located proximate said cache, for containing a copy of physical addresses stored in said primary TLB, said physical addresses retrievable from said shadow TLB means thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 7

For use in a processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache, a circuit for increasing a translation speed of said primary TLB, comprising: shadow TLB means, located proximate said cache, for containing a copy of physical addresses stored in said primary TLB, said physical addresses retrievable from said shadow TLB means thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 8

The circuit as recited in claim 5 wherein said cache includes means for storing tags having multiple ones of said shadow TLB means interleaved therein.

Claim 9

The circuit as recited in claim 6 wherein said cache is divided into separate, physically-addressable sectors and said means for storing tags further has tag register means corresponding to each of said sectors.

Claim 10

The circuit as recited in claim 6 wherein said means for storing tags further has at least one tag register means and means for comparing said multiple ones of said shadow TLB means with said at least one tag register means.

Claim 11

For use in a processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache, a method of increasing a translation speed of said primary TLB, comprising the steps of: making a copy of physical addresses stored in said primary TLB in a shadow TLB located proximate said cache; and retrieving said physical addresses from said shadow TLB thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 12

For use in a processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache, a method of increasing a translation speed of said primary TLB, comprising the steps of: making a copy of physical addresses stored in said primary TLB in a shadow TLB located proximate said cache; and retrieving said physical addresses from said shadow TLB thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 13

The method as recited in claim 9 wherein said step of making comprises the step of making multiple copies of said physical addresses in interleaved locations in a tag array of said cache.

Claim 14

The method as recited in claim 10 wherein said cache is divided into separate, physically-addressable sectors and said tag array further has a tag register corresponding to each of said sectors.

Claim 15

The method as recited in claim 10 wherein said tag array further has at least one tag register, said method further comprising the step of comparing said multiple ones of said shadow TLB means with said at least one tag register means.

Claim 16

A computer system, comprising: (a) a pipelined processor having at least one execution pipeline for executing instructions, said execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages; (b) system memory for storing data or instructions; (c) a physically-addressable cache for storing portions of said data or ones of said instructions; (d) a translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache; (e) said processor including fetch logic that fetches said portions of said data or said ones of said instructions from said system memory; and (f) said processor further including a circuit for increasing a translation speed of said primary TLB, including: (i) a shadow TLB, located proximate said cache, that contains a copy of physical addresses stored in said primary TLB, said physical addresses retrievable from said shadow TLB thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 17

A computer system, comprising: (a) a pipelined processor having at least one execution pipeline for executing instructions, said execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages; (b) system memory for storing data or instructions; (c) a physically-addressable cache for storing portions of said data or ones of said instructions; (d) a translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing said cache; (e) said processor including fetch logic that fetches said portions of said data or said ones of said instructions from said system memory; and (f) said processor further including a circuit for increasing a translation speed of said primary TLB, including: (i) a shadow TLB, located proximate said cache, that contains a copy of physical addresses stored in said primary TLB, said physical addresses retrievable from said shadow TLB thereby avoiding logic circuitry interposed between said primary TLB and said cache.

Claim 18

The system as recited in claim 13 wherein said cache includes a tag array having multiple ones of said shadow TLB interleaved therein.

Claim 19

The system as recited in claim 14 wherein said cache is divided into separate, physically-addressable sectors and said tag array further has tag registers corresponding to each of said sectors.

Claim 20

The system as recited in claim 14 wherein said tag array further has at least one tag register and comparison circuitry that compares said multiple ones of said shadow TLB with said at least one tag register.

Claim 23

The method as recited in claim 17 wherein said cache includes a tag array having multiple ones of said shadow TLB interleaved therein.

Claim 24

The method as recited in claim 18 wherein said cache is divided into separate, physically-addressable sectors and said tag array further has tag registers corresponding to each of said sectors.

Claim 25

The method as recited in claim 19 wherein said tag array further has at least one tag register and comparison circuitry that compares said multiple ones of said shadow TLB with said at least one tag register.