Patent US6172387B1 successfully refreshed from Google Patents.
US6172387B1
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US
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Semiconductor interconnection structure and method
Assignee: Micron Technology Inc
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Filing: 1998-05-04
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Granted: 2001-01-09
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Expires: 2018-05-04
Abstract
Abstract A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.
Inventors
- 👤 Randhir P. S. Thakur
- 👤 Jeff Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:48
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10W; H10W20/00; H10W20/01; H10W20/031; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/315; H10B12/48
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
72 words
A memory storage and transfer system comprising: a memory storage area having cell capacitors containing a lower electrode layer, an upper electrode layer, and a dielectric layer between said lower and upper electrode layers; a peripheral circuit area having first and second interconnection layers and a dielectric layer between said first and second interconnection layers, wherein said lower electrode layer and said first interconnection layer are formed from the same material layer.
Claim 2
Dependent Claim
72 words
A memory storage and transfer system comprising: a memory storage area having cell capacitors containing a lower electrode layer, an upper electrode layer, and a dielectric layer between said lower and upper electrode layers; a peripheral circuit area having first and second interconnection layers and a dielectric layer between said first and second interconnection layers, wherein said lower electrode layer and said first interconnection layer are formed from the same material layer.
Claim 3
Dependent Claim
27 words
The memory storage and transfer system of claim 1 , wherein said upper electrode layer and said second interconnection layer are formed from the same material layer.
Claim 4
Dependent Claim
26 words
The memory storage and transfer system of claim 2 , wherein at least one of said first and second interconnection layers is a conductive oxide layer.
Claim 5
Dependent Claim
30 words
The memory storage and transfer system of claim 3 , wherein said conductive oxide layer is a material selected from the group consisting of RuO 2 and IrO 2 .
Claim 6
Dependent Claim
36 words
The memory storage and transfer system of claim 2 , wherein at least one of said first and second interconnection layers is a material selected from the group consisting of Ru, Ir and PtSi 2 .
Claim 7
Dependent Claim
44 words
The memory storage and transfer system of claim 2 , wherein at least one of said first and second interconnection layers is a material selected from the group consisting of WSi 2 , Al, Al 2 O 3 , Ti, TiN, Pt, and W.
Claim 8
Dependent Claim
42 words
The memory storage and transfer system of claim 2 , wherein at least a portion of said dielectric layer in said memory storage area has a different composition from at least a portion of said dielectric layer in said peripheral circuit area.
Claim 9
Dependent Claim
48 words
The memory storage and transfer system of claim 7 , wherein said portion of said dielectric layer covering said memory storage area is comprised of a high K dielectric and said portion of said dielectric layer covering said peripheral circuit area is comprised of a low K dielectric.
Claim 10
Dependent Claim
47 words
The memory storage and transfer system of claim 7 , wherein at least one of said portions of said dielectric layer is a material selected from the group consisting of ST, BST, PZT , SBT, TaO 5 , TiO 2 , and T 2 O 3 .
Claim 11
Dependent Claim
96 words
A memory device including a memory cell array area and a peripheral circuit area, said memory device comprising: a first conductive layer formed in said peripheral circuit area and said memory cell array area, wherein said first conductive layer is patterned as a capacitor lower electrode in said memory cell array area and as a first interconnection layer in said peripheral circuit area; and at least one dielectric layer formed over said capacitor lower electrode and said first interconnection layer to insulate said capacitor lower electrode and said first interconnection layer from an overlying conductive layer.
Claim 12
Dependent Claim
96 words
A memory device including a memory cell array area and a peripheral circuit area, said memory device comprising: a first conductive layer formed in said peripheral circuit area and said memory cell array area, wherein said first conductive layer is patterned as a capacitor lower electrode in said memory cell array area and as a first interconnection layer in said peripheral circuit area; and at least one dielectric layer formed over said capacitor lower electrode and said first interconnection layer to insulate said capacitor lower electrode and said first interconnection layer from an overlying conductive layer.
Claim 13
Dependent Claim
65 words
The memory device of claim 10 , wherein said memory device further comprises: a second conductive layer formed over said at least one dielectric layer in said peripheral circuit area and said memory cell array area, wherein said second conductive layer is patterned as a capacitor upper electrode in said memory cell array area and as a second interconnection layer in said peripheral circuit area.
Claim 14
Dependent Claim
24 words
The memory device of claim 11 , wherein at least one of said first and second interconnection layers is comprised of a conductive oxide.
Claim 15
Dependent Claim
24 words
The memory device of claim 12 , wherein said conductive oxide is selected from the group consisting of RuO 2 and IrO 2 .
Claim 16
Dependent Claim
33 words
The memory device of claim 11 , wherein at least one of said first and second conductive layers is a material selected from the group consisting of Ru, Ir and PtSi 2 .
Claim 17
Dependent Claim
41 words
The memory device of claim 11 , wherein at least one of said first and second conductive layers is a material selected from the group consisting of WSi 2 , Al, Al 2 O 3 , Ti, TiN, Pt, and W.
Claim 18
Dependent Claim
29 words
The memory device of claim 10 , wherein said dielectric layer in said memory storage area has a different composition from said dielectric layer in said peripheral circuit area.
Claim 19
Dependent Claim
38 words
The memory device of claim 16 , wherein said dielectric layer in said memory cell array is comprised of a high K dielectric and said dielectric layer in said peripheral circuit is comprised of a low K dielectric.
Claim 20
Dependent Claim
37 words
The memory device of claim 10 , wherein said dielectric layer is a material selected from the group consisting of ST, BST, PZT , SBT, TaO 5 , TiO 2 , and T 2 O 3 .
Claim 21
Dependent Claim
110 words
A computer memory system comprising: a memory cell array having an upper electrode layer and a lower electrode layer, a peripheral circuit area having first and second interconnection layers, wherein said first interconnection layer is formed of the same material layer as said lower electrode layer and said second interconnection layer is formed from the same material layer as said upper electrode layer, a first dielectric film between said upper and lower electrode layers, wherein said first dielectric film is comprised of a high K dielectric, and a second dielectric film between said first and second interconnection layers, wherein said second dielectric film is comprised of a low K dielectric.
Claim 22
Dependent Claim
110 words
A computer memory system comprising: a memory cell array having an upper electrode layer and a lower electrode layer, a peripheral circuit area having first and second interconnection layers, wherein said first interconnection layer is formed of the same material layer as said lower electrode layer and said second interconnection layer is formed from the same material layer as said upper electrode layer, a first dielectric film between said upper and lower electrode layers, wherein said first dielectric film is comprised of a high K dielectric, and a second dielectric film between said first and second interconnection layers, wherein said second dielectric film is comprised of a low K dielectric.
Claim 23
Dependent Claim
23 words
The computer memory system of claim 19 , wherein at least one of said upper and lower electrode layers is a conductive oxide.
Claim 24
Dependent Claim
25 words
The computer memory system of claim 20 , wherein said conductive oxide is selected from the group consisting of RuO 2 and IrO 2 .
Claim 25
Dependent Claim
34 words
The computer memory system of claim 19 , wherein at least one of said upper and lower electrode layers is a material selected from the group consisting of Ru, Ir and PtSi 2 .
Claim 26
Dependent Claim
42 words
The computer memory system of claim 19 , wherein at least one of said upper and lower electrode layers is a material selected from the group consisting of WSi 2 , Al, Al 2 O 3 , Ti, TiN, Pt, and W.
Claim 27
Dependent Claim
74 words
A memory storage and transfer system comprising: a memory storage area having cell capacitors containing a lower electrode layer, an upper electrode layer, and a first dielectric layer between said lower and upper electrode layers; a peripheral circuit area having first and second interconnection layers and a second dielectric layer between said first and second interconnection layers, wherein said lower electrode layer and said first interconnection layer are formed from the same material layer.
Claim 28
Dependent Claim
74 words
A memory storage and transfer system comprising: a memory storage area having cell capacitors containing a lower electrode layer, an upper electrode layer, and a first dielectric layer between said lower and upper electrode layers; a peripheral circuit area having first and second interconnection layers and a second dielectric layer between said first and second interconnection layers, wherein said lower electrode layer and said first interconnection layer are formed from the same material layer.
Claim 29
Dependent Claim
27 words
The memory storage and transfer system of claim 24 , wherein said upper electrode layer and said second interconnection layer are formed from the same material layer.
Claim 30
Dependent Claim
26 words
The memory storage and transfer system of claim 25 , wherein at least one of said first and second interconnection layers is a conductive oxide layer.
Claim 31
Dependent Claim
30 words
The memory storage and transfer system of claim 26 , wherein said conductive oxide layer is a material selected from the group consisting of RuO 2 and IrO 2 .
Claim 32
Dependent Claim
44 words
The memory storage and transfer system of claim 25 , wherein at least a portion of said first dielectric layer in said memory storage area has a different composition from at least a portion of said second dielectric layer in said peripheral circuit area.
Claim 33
Dependent Claim
50 words
The memory storage and transfer system of claim 28 , wherein said portion of said first dielectric layer in said memory storage area is comprised of a high K dielectric and said portion of said second dielectric layer in said peripheral circuit area is comprised of a low K dielectric.
Claim 34
Dependent Claim
47 words
The memory storage and transfer system of claim 24 , wherein at least one of said first and second dielectric layers is a material selected from the group consisting of ST, BST, PZT , SBT, TaO 5 , TiO 2 , and T 2 O 3 .
Claim 35
Dependent Claim
102 words
A memory device including a memory cell array area and a peripheral circuit area, said memory device comprising: a first conductive layer formed in said peripheral circuit area and said memory cell array area, wherein said first conductive layer is patterned as a capacitor lower electrode in said memory cell array area and as a first interconnection layer in said peripheral circuit area; and at least one first dielectric layer portion formed on said first conductive layer in said memory cell array area and at least one second dielectric layer portion formed on said first conductive layer in said peripheral circuit area.
Claim 36
Dependent Claim
102 words
A memory device including a memory cell array area and a peripheral circuit area, said memory device comprising: a first conductive layer formed in said peripheral circuit area and said memory cell array area, wherein said first conductive layer is patterned as a capacitor lower electrode in said memory cell array area and as a first interconnection layer in said peripheral circuit area; and at least one first dielectric layer portion formed on said first conductive layer in said memory cell array area and at least one second dielectric layer portion formed on said first conductive layer in said peripheral circuit area.
Claim 37
Dependent Claim
59 words
The memory device of claim 31 , further comprising a second conductive layer formed over said first and second dielectric layer portions in said peripheral circuit area and said memory cell array area and which is patterned as a capacitor upper electrode in said memory cell array area and as a second interconnection layer in said peripheral circuit area.
Claim 38
Dependent Claim
24 words
The memory device of claim 32 , wherein at least one of said first and second interconnection layers is comprised of a conductive oxide.
Claim 39
Dependent Claim
24 words
The memory device of claim 33 , wherein said conductive oxide is selected from the group consisting of RuO 2 and IrO 2 .
Claim 40
Dependent Claim
34 words
The memory device of claim 31 , wherein said first dielectric layer portion in said memory cell array area has a different composition from said second dielectric layer portion in said peripheral circuit area.
Claim 41
Dependent Claim
44 words
The memory device of claim 35 , wherein said first dielectric layer portion in said memory cell array area is comprised of a high K dielectric and said second dielectric layer portion in said peripheral circuit area is comprised of a low K dielectric.
Claim 42
Dependent Claim
44 words
The memory device of claim 31 , wherein at least one of said first and second dielectric layer portions is a material selected from the group consisting of ST, BST, PZT, SBT, TaO 5 , TiO 2 , and T 2 O 3 .
Claim 43
Dependent Claim
110 words
A computer memory system comprising: a memory cell array having an upper electrode layer and a lower electrode layer, a peripheral circuit area having first and second interconnection layers, wherein said first interconnection layer is formed from the same material layer as said lower electrode layer and said second interconnection layer is formed from the same material layer as said upper electrode layer, a first dielectric film between said upper and lower electrode layers, wherein said first dielectric film is comprised of a high K dielectric, and a second dielectric film between said first and second interconnection layers, wherein said second dielectric film is comprised of a low K dielectric.
Claim 44
Dependent Claim
110 words
A computer memory system comprising: a memory cell array having an upper electrode layer and a lower electrode layer, a peripheral circuit area having first and second interconnection layers, wherein said first interconnection layer is formed from the same material layer as said lower electrode layer and said second interconnection layer is formed from the same material layer as said upper electrode layer, a first dielectric film between said upper and lower electrode layers, wherein said first dielectric film is comprised of a high K dielectric, and a second dielectric film between said first and second interconnection layers, wherein said second dielectric film is comprised of a low K dielectric.
Claim 45
Dependent Claim
23 words
The computer memory system of claim 38 , wherein at least one of said upper and lower electrode layers is a conductive oxide.
Claim 46
Dependent Claim
25 words
The computer memory system of claim 39 , wherein said conductive oxide is selected from the group consisting of RuO 2 and IrO 2 .
References Cited (Backward Citations)
US5399890A
Cited
US5903492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |