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US6170072B1
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US
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Logic circuit verification apparatus and method for semiconductor integrated circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1998-11-30
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Granted: 2001-01-02
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Expires: 2018-11-30
Abstract
Abstract There is constituted a logic circuit verification apparatus designed for checking a semiconductor integrated circuit including a core and a new circuit. The core has a internal circuit in which logic and timing have already been verified. The apparatus is provided with a section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit. The apparatus is also provided with a section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit. At the time of simulation, predetermined processing is performed solely with regard to the extracted cells.
Inventors
- 👤 Yasuo Moriguchi
- 👤 Toshinori Inoshita
- 👤 Yoshio Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3016
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A logic circuit verification apparatus which performs logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core, said logic circuit verification apparatus comprising: a timing cell extraction section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and a delay cell extraction section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
Claim 2
Dependent Claim
126 words
A logic circuit verification apparatus which performs logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core, said logic circuit verification apparatus comprising: a timing cell extraction section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and a delay cell extraction section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
Claim 3
Dependent Claim
77 words
The logic circuit verification apparatus as defined in claim 1 , further comprising: a non-verified cell extraction section for extracting as non-verified cells from the cells of the core cells which are required to be subjected to neither timing verification nor time delay calculation when the core is used in combination with the new circuit; and a function cell replacement section which replaces information regarding the non-verified cells with information regarding solely the function of the cells.
Claim 4
Dependent Claim
76 words
The logic circuit verification apparatus as defined in claim 1 , further comprising: a non-verified cell extraction section for extracting as non-verified cells from the cells of the core cells which are required to be subjected to neither timing verification nor time delay calculation when the core is used in combination with the new circuit; and an RTL description conversion section which converts information regarding a module constituted of the non-verified cells into an RTL description.
Claim 5
Dependent Claim
49 words
The logic circuit verification apparatus as defined in claim 1 , further comprising: a timing calculation section which calculates timing verification values with regard to the timing cells; and a simulation section which performs simulation of timing verification of the timing cells through use of the timing verification value.
Claim 6
Dependent Claim
47 words
The logic circuit verification apparatus as defined in claim 1 , further comprising: a delay time calculation section which calculates a delay time with regard to the delay cells; and a simulation section which performs delay simulation of the delay cells through use of the delay time.
Claim 7
Dependent Claim
48 words
The logic circuit verification apparatus as defined in claim 1 , further comprising: a simulation section which performs timing verification of the semiconductor integrated circuit, and an external pin information retaining section which retains information regarding external input pins of the core during execution of the timing verification.
Claim 8
Independent Claim
115 words
A method of logic circuit verification for performing logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core, said method comprising the steps for: extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
Claim 9
Independent Claim
115 words
A method of logic circuit verification for performing logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core, said method comprising the steps for: extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
Claim 10
Dependent Claim
67 words
The method of logic circuit verification as defined in claim 7 , further comprising the steps for: extracting from the cells of the core non-verified cells which are required to be subjected to neither timing verification nor time delay calculation when the core is used in combination with the new circuit; and replacing information regarding the non-verified cells with information regarding solely the function of the cells.
Claim 11
Dependent Claim
66 words
The method of logic circuit verification as. defined in claim 7 , further comprising the steps for: extracting from the cells of the core non-verified cells which are required to be subjected to neither timing verification nor time delay calculation when the core is used in combination with the new circuit; and converting information regarding a module constituted of the non-verified cells into an RTL description.
Claim 12
Dependent Claim
44 words
The method of logic circuit verification as defined in claim 7 , further comprising the steps for: calculating timing verification values with regard to the timing cells; and performing simulation of timing verification of the timing cells through use of the timing verification value.
Claim 13
Dependent Claim
41 words
The method of logic circuit verification as defined in claim 7 , further comprising the steps for: calculating a delay time with regard to, the delay cells; and performing delay simulation of the delay cells through use of the delay time.
Claim 14
Dependent Claim
41 words
The method of logic circuit verification as defined in claim 7 , further comprising the steps for: performing timing verification of the semiconductor integrated circuit, and retaining information regarding external input pins of the core during execution of the timing verification.
References Cited (Backward Citations)
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JPH0660143A
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US5940370A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |