Patent US6167556A successfully refreshed from Google Patents.
US6167556A
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System for logic extraction from a layout database
Assignee: Macronix International Co Ltd
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Filing: 1997-10-14
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Granted: 2000-12-26
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Expires: 2017-10-14
Abstract
Abstract A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.
Inventors
- 👤 Albert C. Sun
- 👤 Chee-Horng Lee
- 👤 Chang-Lun Chen
- 👤 Chun-hao Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:33
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
116 words
A process for extraction of logic design information from a transistor level net list stored in memory, comprising: processing with data processing resources, the transistor level net list in the memory to define groups of transistors in the transistor level net list, according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage, and transistor type; analyzing with the data processing resources, the groups of transistors according to the interconnections of the transistors in the respective groups; and identifying with the data processing resources, logic units in response to the step of analyzing.
Claim 2
Dependent Claim
116 words
A process for extraction of logic design information from a transistor level net list stored in memory, comprising: processing with data processing resources, the transistor level net list in the memory to define groups of transistors in the transistor level net list, according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage, and transistor type; analyzing with the data processing resources, the groups of transistors according to the interconnections of the transistors in the respective groups; and identifying with the data processing resources, logic units in response to the step of analyzing.
Claim 3
Dependent Claim
84 words
The process of claim 1, wherein the groups include a first group of transistors of a first type having a source node coupled to a supply voltage, a second group of transistors of the first type having a source node not coupled to a supply voltage, a third group of transistors of a second type having a source node coupled to a reference voltage, and a fourth group of transistors of the second type having a source node not coupled to a reference voltage.
Claim 4
Dependent Claim
80 words
The process of claim 2, wherein the first group consists of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, the second group consists of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, the third group consists of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and the fourth group consists of n-channel MOS transistors having source terminals coupled to a VSS reference voltage.
Claim 5
Dependent Claim
85 words
The process of claim 2, wherein the step of analyzing includes determining for at least one of said groups of transistors, respective sets of transistors for particular transistors in said one group, the respective sets including the particular transistor for the set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective sets are coupled to at least one of the sources and drains of other transistors in said respective sets.
Claim 6
Dependent Claim
49 words
The process of claim 4, wherein the step of identifying includes determining subsets of transistors in said respective sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and classifying the subsets as logic units.
Claim 7
Dependent Claim
35 words
The process of claim 5, wherein the step of classifying includes classifying a subset as an inverter if the subset consists of one transistor from the first group and one transistor from the fourth group.
Claim 8
Dependent Claim
45 words
The process of claim 5, wherein the step of classifying includes classifying a subset as a NAND gate having n inputs, if the subset consists of n transistors from the first group, n-I transistor(s) from the third group, and one transistor from the fourth group.
Claim 9
Dependent Claim
45 words
The process of claim 5, wherein the step of classifying includes classifying a subset as a NOR gate having n inputs, if the subset consists of one transistor from the first group, n-1 transistor(s) from the second group, and n transistors from the fourth group.
Claim 10
Dependent Claim
16 words
The process of claim 1, wherein said logic units include inverters, NAND gates, and NOR gates.
Claim 11
Dependent Claim
16 words
The process of claim 9, wherein said logic units include latches, pass gates and flip flops.
Claim 12
Dependent Claim
30 words
The process of claim 10, wherein the transistor level net list describes elements of a logic block and said logic units include input and output nodes of the logic block.
Claim 13
Dependent Claim
23 words
The process of claim 1, including producing a computer readable, gate level description of the logic in response to the identified logic units.
Claim 14
Independent Claim
121 words
A system for extraction of logic design information from a transistor level net list stored in memory, comprising: data processing resources which process the transistor level net list in the memory to define groups of transistors in the transistor level net list, according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage, and transistor type; data processing resources which analyze the groups of transistors according to the interconnections of the transistors in the respective groups to define interconnected sets of transistors; and data processing resources which identify logic units in response to the interconnected sets of transistors.
Claim 15
Independent Claim
121 words
A system for extraction of logic design information from a transistor level net list stored in memory, comprising: data processing resources which process the transistor level net list in the memory to define groups of transistors in the transistor level net list, according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage, and transistor type; data processing resources which analyze the groups of transistors according to the interconnections of the transistors in the respective groups to define interconnected sets of transistors; and data processing resources which identify logic units in response to the interconnected sets of transistors.
Claim 16
Dependent Claim
84 words
The system of claim 13, wherein the groups include a first group of transistors of a first type having a source node coupled to a supply voltage, a second group of transistors of the first type having a source node not coupled to a supply voltage, a third group of transistors of a second type having a source node not coupled to a reference voltage, and a fourth group of transistors of the second type having a source node coupled to a reference voltage.
Claim 17
Dependent Claim
81 words
The system of claim 14, wherein the first group consists of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, the second group consists of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, the third group consists of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and the fourth group consists of n-channel MOS transistors having source terminals coupled to a V SS reference voltage.
Claim 18
Dependent Claim
97 words
The system of claim 14, wherein the data processing resources which analyze the groups include resources which determine for at least one of said groups of transistors, respective interconnected sets of transistors for particular transistors in said one group, the respective interconnected sets including the particular transistor for the respective interconnected set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective interconnected sets are coupled to at least one of the sources and drains of other transistors in said respective interconnected sets.
Claim 19
Dependent Claim
57 words
The system of claim 16, wherein the data processing resources which analyze the groups include resources which determine subsets of transistors in said respective interconnected sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and which classify the subsets as logic units.
Claim 20
Dependent Claim
41 words
The system of claim 16, wherein the data processing resources which classify the subsets include resources which classify a subset as an inverter if the subset consists of one transistor from the first group and one transistor from the fourth group.
Claim 21
Dependent Claim
51 words
The system of claim 16, wherein the data processing resources which classify the subsets include resources which classify a subset as a NAND gate having n inputs, if the subset consists of n transistors from the first group, n-1 transistor(s) from the third group, and one transistor from the fourth group.
Claim 22
Dependent Claim
51 words
The system of claim 16, wherein the data processing resources which classify the subsets include resources which classify a subset as a NOR gate having n inputs, if the subset consists of one transistor from the first group, n-1 transistor(s) from the second group, and n transistors from the fourth group.
Claim 23
Dependent Claim
16 words
The system of claim 13, wherein said logic units include inverters, NAND gates, and NOR gates.
Claim 24
Dependent Claim
16 words
The system of claim 21, wherein said logic units include latches, pass gates and flip flops.
Claim 25
Dependent Claim
30 words
The system of claim 22, wherein the transistor level net list describes elements of a logic block and said logic units include input and output nodes of the logic block.
Claim 26
Dependent Claim
31 words
The system of claim 13, including resources which produce a computer readable, gate level description of logic defined by the transistor level gate list in response to the identified logic units.
Claim 27
Dependent Claim
233 words
A process for extraction of logic design information from a transistor level net list stored in memory, comprising: processing with data processing resources, the transistor level net list in the memory to define groups of transistors in the transistor level net list, wherein the groups include a first group consisting of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, a second group consisting of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, a third group consisting of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and a fourth group consisting of n-channel MOS transistors having source terminals coupled to a V SS reference voltage; determining for at least one of said groups of transistors, respective sets of transistors for particular transistors in said one group, the respective sets including the particular transistor for the set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective sets are coupled to at least one of the sources and drains of other transistors in said respective sets; determining subsets of transistors in said respective sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and classifying the subsets as logic units.
Claim 28
Dependent Claim
233 words
A process for extraction of logic design information from a transistor level net list stored in memory, comprising: processing with data processing resources, the transistor level net list in the memory to define groups of transistors in the transistor level net list, wherein the groups include a first group consisting of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, a second group consisting of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, a third group consisting of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and a fourth group consisting of n-channel MOS transistors having source terminals coupled to a V SS reference voltage; determining for at least one of said groups of transistors, respective sets of transistors for particular transistors in said one group, the respective sets including the particular transistor for the set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective sets are coupled to at least one of the sources and drains of other transistors in said respective sets; determining subsets of transistors in said respective sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and classifying the subsets as logic units.
Claim 29
Dependent Claim
35 words
The process of claim 25, wherein the step of classifying includes classifying a subset as an inverter if the subset consists of one transistor from the first group and one transistor from the fourth group.
Claim 30
Dependent Claim
45 words
The process of claim 25, wherein the step of classifying includes classifying a subset as a NAND gate having n inputs, if the subset consists of n transistors from the first group, n-1 transistor(s) from the third group, and one transistor from the fourth group.
Claim 31
Dependent Claim
45 words
The process of claim 25, wherein the step of classifying includes classifying a subset as a NOR gate having n inputs, if the subset consists of one transistor from the first group, n-1 transistor(s) from the second group, and n transistors from the fourth group.
Claim 32
Dependent Claim
16 words
The process of claim 25, wherein said logic units include inverters, NAND gates, and NOR gates.
Claim 33
Dependent Claim
16 words
The process of claim 29, wherein said logic units include latches, pass gates and flip flops.
Claim 34
Dependent Claim
30 words
The process of claim 30, wherein the transistor level net list describes elements of a logic block and said logic units include input and output nodes of the logic block.
Claim 35
Dependent Claim
23 words
The process of claim 25, including producing a computer readable, gate level description of the logic in response to the identified logic units.
Claim 36
Independent Claim
286 words
A system for extraction of logic design information from a transistor level net list stored in memory, comprising: data processing resources which process the transistor level net list in the memory to define groups of transistors in the transistor level net list, including a first group consists of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, a second group consists of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, a third group consists of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and a fourth group consists of n-channel MOS transistors having source terminals coupled to a V SS reference voltage; data processing resources which analyze the groups of transistors according to the interconnections of the transistors in the respective groups to define interconnected sets of transistors, including resources which determine for at least one of said groups of transistors, respective interconnected sets of transistors for particular transistors in said one group, the respective interconnected sets including the particular transistor for the respective interconnected set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective interconnected sets are coupled to at least one of the sources and drains of other transistors in said respective interconnected sets; and data processing resources which identify logic units in response to the interconnected sets of transistors including resources which determine subsets of transistors in said respective interconnected sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and which classify the subsets as logic units.
Claim 37
Independent Claim
286 words
A system for extraction of logic design information from a transistor level net list stored in memory, comprising: data processing resources which process the transistor level net list in the memory to define groups of transistors in the transistor level net list, including a first group consists of p-channel MOS transistors having source terminals coupled to a V DD supply voltage, a second group consists of p-channel MOS transistors having source terminals not coupled to a V DD supply voltage, a third group consists of n-channel MOS transistors having source terminals not coupled to a V SS reference voltage, and a fourth group consists of n-channel MOS transistors having source terminals coupled to a V SS reference voltage; data processing resources which analyze the groups of transistors according to the interconnections of the transistors in the respective groups to define interconnected sets of transistors, including resources which determine for at least one of said groups of transistors, respective interconnected sets of transistors for particular transistors in said one group, the respective interconnected sets including the particular transistor for the respective interconnected set, and transistors from said first through fourth groups for which at least one of the sources and drains of the transistors in said respective interconnected sets are coupled to at least one of the sources and drains of other transistors in said respective interconnected sets; and data processing resources which identify logic units in response to the interconnected sets of transistors including resources which determine subsets of transistors in said respective interconnected sets, the subsets consisting of transistors in one of said groups which share a gate terminal with a transistor in another of said groups, and which classify the subsets as logic units.
Claim 38
Dependent Claim
41 words
The system of claim 33, wherein the data processing resources which classify the subsets include resources which classify a subset as an inverter if the subset consists of one transistor from the first group and one transistor from the fourth group.
Claim 39
Dependent Claim
51 words
The system of claim 33, wherein the data processing resources which classify the subsets include resources which classify a subset as a NAND gate having n inputs, if the subset consists of n transistors from the first group, n-1 transistor(s) from the third group, and one transistor from the fourth group.
Claim 40
Dependent Claim
51 words
The system of claim 33, wherein the data processing resources which classify the subsets include resources which classify a subset as a NOR gate having n inputs, if the subset consists of one transistor from the first group, n-1 transistor(s) from the second group, and n transistors from the fourth group.
Claim 41
Dependent Claim
16 words
The system of claim 33, wherein said logic units include inverters, NAND gates, and NOR gates.
Claim 42
Dependent Claim
16 words
The system of claim 37, wherein said logic units include latches, pass gates and flip flops.
Claim 43
Dependent Claim
30 words
The system of claim 38, wherein the transistor level net list describes elements of a logic block and said logic units include input and output nodes of the logic block.
Claim 44
Dependent Claim
31 words
The system of claim 33, including resources which produce a computer readable, gate level description of logic defined by the transistor level gate list in response to the identified logic units.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |