Class-ab output stages with improved distortion performance

Claim 2

An output stage with improved distortion performance, the output stage comprising: a buffer output circuit having a signal input, a non-buffered signal output and a buffered signal output; a feed-forward control circuit having a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit; and a bias circuit having a bias output coupled to the control input of the feed-forward control circuit wherein a signal generated at said bias output is operable to constantly bias said feed-forward control circuit into a low-distortion operating state regardless of a value of said buffered signal output.

Claim 3

An output stage as recited in claim 1 wherein the buffer output circuit includes a complementary 4-transistor emitter follower having an output.

Claim 4

An output stage as recited in claim 2 wherein the feed-forward control circuit includes first and second complementary common emitter devices.

Claim 5

An output stage as recited in claim 3 wherein the output of the complementary 4-transistor emitter follower is coupled in parallel with the first and second complementary common emitter devices.

Claim 6

An output stage as recited in claim 4 wherein the bias circuit includes a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output.

Claim 7

An output stage as recited in claim 5 wherein the bias power source includes two parallel coupled current mirrors.

Claim 8

An output stage as recited in claim 5 wherein the bias signal operates to electrically bias the feed-forward control circuit towards a control position that experiences less distortion than a non-biased control position.

Claim 9

An output stage as recited in claim 1 wherein the bias circuit includes a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output.

Claim 10

An output stage as recited in claim 8 wherein the bias power source includes two parallel coupled current mirrors.

Claim 11

An output stage as recited in claim 8 wherein the bias signal operates to electrically bias the feed-forward control circuit towards a control position that experiences less distortion than a non-biased control position.

Claim 12

An output stage with certain distortion performance characteristics, the output stage comprising: a buffer output circuit formed with a signal input, a non-buffered signal output and a buffered signal output, the buffer output circuit including a complementary 4-transistor emitter follower having an output; a feed-forward control circuit formed with a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit, the feed-forward control circuit including first and second complementary common emitter devices; and a bias circuit formed with a bias output coupled to the control input of the feed-forward control circuit, the bias output including a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output said bias signal operable to constantly bias said feed-forward control circuit into a low-distortion operating state regardless of a value of said buffered signal output.

Claim 13

An output stage with certain distortion performance characteristics, the output stage comprising: a buffer output circuit formed with a signal input, a non-buffered signal output and a buffered signal output, the buffer output circuit including a complementary 4-transistor emitter follower having an output; a feed-forward control circuit formed with a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit, the feed-forward control circuit including first and second complementary common emitter devices; and a bias circuit formed with a bias output coupled to the control input of the feed-forward control circuit, the bias output including a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output said bias signal operable to constantly bias said feed-forward control circuit into a low-distortion operating state regardless of a value of said buffered signal output.

Claim 14

An output stage as recited in claim 11, wherein the buffer output circuit further includes a pair of near perfect current sources providing a power supply.

Claim 15

An output stage as recited in claim 11 wherein the buffer output circuit is a class-AB type output stage.

Claim 16

An output stage as recited in claim 13 wherein the feed-forward control circuit includes a pair of common emitter transistor devices driven by a pair of source and sink current devices.

Claim 17

An output stage as recited in claim 11 wherein the feed-forward control circuit includes a pair of common emitter transistor devices driven by a pair of source and sink current devices.

Claim 18

An output stage as recited in claim 15 wherein the feed-forward control circuit includes two parallel connected driver transistors and a complementary pair of constant current transistors, the complementary pair of constant current transistors being operated as current mirrors together with four helper transistors.

Claim 19

An output stage with certain distortion performance characteristics, the output stage comprising: a buffer output circuit formed with a signal input, a non-buffered signal output and a buffered signal output, the buffer output circuit including a complimentary 4-transistor emitter follower having an output; a feed-forward control circuit formed with a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit, the feed-forward control circuit including first and second complimentary common emitter devices; and a bias circuit formed with a bias output coupled to the control input of the feed-forward control unit, the bias output including a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output. wherein the bias signal generated at the bias circuit bias output is a constant bias current forcing the feed-forward current devices into a certain minimum distortion state, and wherein the bias circuit includes source and sink current devices, constant current transistors coupled within current mirrors formed with two helper transistor devices, and two diode connected transistors.

Claim 20

An output stage with certain distortion performance characteristics, the output stage comprising: a buffer output circuit formed with a signal input, a non-buffered signal output and a buffered signal output, the buffer output circuit including a complimentary 4-transistor emitter follower having an output; a feed-forward control circuit formed with a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit, the feed-forward control circuit including first and second complimentary common emitter devices; and a bias circuit formed with a bias output coupled to the control input of the feed-forward control unit, the bias output including a controllable bias power source, the bias power source generating a bias signal at the bias circuit bias output. wherein the bias signal generated at the bias circuit bias output is a constant bias current forcing the feed-forward current devices into a certain minimum distortion state, and wherein the bias circuit includes source and sink current devices, constant current transistors coupled within current mirrors formed with two helper transistor devices, and two diode connected transistors.

Claim 21

A feed-forward control method for improving performance of a 4-transistor emitter follower comprising: providing a buffer output circuit having a signal input, a non-buffered signal output and a buffered signal output; providing a feed-forward control circuit having a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit; providing a bias signal to said control input of said feed-forward control circuit, said bias signal operable to constantly bias said feed-forward circuit into a low-distortion operating state regardless of a value of said buffered signal output.

Claim 22

A feed-forward control method for improving performance of a 4-transistor emitter follower comprising: providing a buffer output circuit having a signal input, a non-buffered signal output and a buffered signal output; providing a feed-forward control circuit having a control input and a control output, the control input coupled to the non-buffered signal output of the buffer output circuit, and the control output coupled to the buffered signal output of the buffer output circuit; providing a bias signal to said control input of said feed-forward control circuit, said bias signal operable to constantly bias said feed-forward circuit into a low-distortion operating state regardless of a value of said buffered signal output.