Control circuit and method for maintaining high efficiency in a buck-boost switching regulator

Claim 3

The method defined in claim 1 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal, wherein the first and second drive signals are generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal, wherein the third and fourth drive signals are generated in response to the second control signal.

Claim 4

The method defined in claim 2 wherein providing the first and the second periodic waveform signals further comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a direct current offset voltage.

Claim 5

The method defined in claim 2 wherein generating the first and the second voltage signals further comprises generating the second voltage signal offset from the first voltage signal by a direct current offset voltage.

Claim 6

The method defined in claim 2 wherein providing the first and the second periodic waveform signals further comprises providing the first and the second periodic waveform signals that have the same wave shape and the same peak-to-peak amplitude.

Claim 7

The method defined in claim 2 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different wave shape than the first periodic waveform signal.

Claim 8

The method defined in claim 2 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different peak-to-peak amplitude than the first periodic waveform signal.

Claim 9

The method defined in claim 2 wherein the first and second periodic waveform signals are sawtooth waveform signals.

Claim 10

The method defined in claim 2 wherein the first and second periodic waveform signals are triangular waveform signals.

Claim 11

The method defined in claim 1 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal; comparing the second voltage signal with the second periodic waveform signal to generate a second control signal; selecting the first and second control signals to generate a first selected signal, wherein the first selected signal has substantially constant propagation delays and wherein the first and second drive signals are generated in response to the first selected signal; selecting the first and second control signals to generate a second selected signal, wherein the second selected signal has substantially constant propagation delays and wherein the third and fourth drive signals are generated in response to the second selected signal.

Claim 14

The method defined in claim 11 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal, wherein the first drive signal is generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal, wherein the second drive signal is generated in response to the second control signal.

Claim 15

The method defined in claim 12 wherein providing the first and the second periodic waveform signals further comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a direct current offset voltage.

Claim 16

The method defined in claim 12 wherein generating the first and the second voltage signals further comprises generating the second voltage signal offset from the first voltage signal by a direct current offset voltage.

Claim 17

The method defined in claim 12 wherein providing the first and the second periodic waveform signals further comprises providing the first and the second periodic waveform signals that have the same wave shape and the same peak-to-peak amplitude.

Claim 18

The method defined in claim 12 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different wave shape than the first periodic waveform signal.

Claim 19

The method defined in claim 12 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different peak-to-peak amplitude than the first periodic waveform signal.

Claim 20

The method defined in claim 12 wherein the first and second periodic waveform signals are sawtooth waveform signals.

Claim 21

The method defined in claim 12 wherein the first and second periodic waveform signals are triangular waveform signals.

Claim 22

The method defined in claim 11 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal; comparing the second voltage signal with the second periodic waveform signal to generate a second control signal; selecting the first and second control signals to generate a first selected signal, wherein the first selected signal has substantially constant propagation delays and wherein the first drive signal is generated in response to the first selected signal; selecting the first and second control signals to generate a second selected signal, wherein the second selected signal has substantially constant propagation delays and wherein the second drive signal is generated in response to the second selected signal.

Claim 25

The method defined in claim 21 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal, wherein the first and second drive signals are generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal, wherein the third drive signal is generated in response to the second control signal.

Claim 26

The method defined in claim 22 wherein providing the first and the second periodic waveform signals further comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a direct current offset voltage.

Claim 27

The method defined in claim 22 wherein generating the first and the second voltage signals further comprises generating the second voltage signal offset from the first voltage signal by a direct current offset voltage.

Claim 28

The method defined in claim 22 wherein providing the first and the second periodic waveform signals further comprises providing the first and the second periodic waveform signals that have the same wave shape and the same peak-to-peak amplitude.

Claim 29

The method defined in claim 22 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different wave shape than the first periodic waveform signal.

Claim 30

The method defined in claim 22 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different peak-to-peak amplitude than the first periodic waveform signal.

Claim 31

The method defined in claim 22 wherein the first and second periodic waveform signals are sawtooth waveform signals.

Claim 32

The method defined in claim 22 wherein the first and second periodic waveform signals are triangular waveform signals.

Claim 33

The method defined in claim 21 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal; comparing the second voltage signal with the second periodic waveform signal to generate a second control signal; selecting the first and second control signals to generate a first selected signal, wherein the first selected signal has substantially constant propagation delays and wherein the first and second drive signals are generated in response to the first selected signal; selecting the first and second control signals to generate a second selected signal, wherein the second selected signal has substantially constant propagation delays and wherein the third drive signal is generated in response to the second selected signal.

Claim 36

The method defined in claim 31 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal, wherein the first drive signal is generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal, wherein the second and third drive signals are generated in response to the second control signal.

Claim 37

The method defined in claim 32 wherein providing the first and the second periodic waveform signals further comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a direct current offset voltage.

Claim 38

The method defined in claim 32 wherein generating the first and the second voltage signals further comprises generating the second voltage signal offset from the first voltage signal by a direct current offset voltage.

Claim 39

The method defined in claim 32 wherein providing the first and the second periodic waveform signals further comprises providing the first and the second periodic waveform signals that have the same wave shape and the same peak-to-peak amplitude.

Claim 40

The method defined in claim 32 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different wave shape than the first periodic waveform signal.

Claim 41

The method defined in claim 32 wherein providing the first and the second periodic waveform signals further comprises providing the second periodic waveform signal that has a different peak-to-peak amplitude than the first periodic waveform signal.

Claim 42

The method defined in claim 32 wherein the first and second periodic waveform signals are sawtooth waveform signals.

Claim 43

The method defined in claim 32 wherein the first and second periodic waveform signals are triangular waveform signals.

Claim 44

The method defined in claim 31 further comprising: generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; comparing the first voltage signal with the first periodic waveform signal to generate a first control signal; comparing the second voltage signal with the second periodic waveform signal to generate a second control signal; selecting the first and second control signals to generate a first selected signal, wherein the first selected signal has substantially constant propagation delays and wherein the first drive signal is generated in response to the first selected signal; selecting the first and second control signals to generate a second selected signal, wherein the second selected signal has substantially constant propagation delays and wherein the second and third drive signals are generated in response to the second selected signal.

Claim 45

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a second switch coupled between the first terminal of the inductor and GROUND, a third switch coupled between a second terminal of the inductor and GROUND, and a fourth switch coupled between the second terminal of the inductor and the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, third, and fourth outputs coupled to the first, second, third, and fourth switches, respectively, wherein the first switch is OFF when the second switch is ON, the second switch is OFF when the first switch is ON, the third switch is OFF when the fourth switch is ON, and the fourth switch is OFF when the third switch is ON.

Claim 46

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a second switch coupled between the first terminal of the inductor and GROUND, a third switch coupled between a second terminal of the inductor and GROUND, and a fourth switch coupled between the second terminal of the inductor and the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, third, and fourth outputs coupled to the first, second, third, and fourth switches, respectively, wherein the first switch is OFF when the second switch is ON, the second switch is OFF when the first switch is ON, the third switch is OFF when the fourth switch is ON, and the fourth switch is OFF when the third switch is ON.

Claim 47

The control circuit defined in claim 41 wherein a direct current offset is created between the third and fourth output nodes of the signal generator circuitry.

Claim 48

The control circuit defined in claim 42 wherein the signal generator circuitry further comprises a resistor coupled between the third and fourth output nodes, and a current source coupled between the fourth output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 49

The control circuit defined in claim 41 wherein a direct current offset is created between the first and second output nodes of the signal generator circuitry.

Claim 50

The control circuit defined in claim 44 wherein the signal generator circuitry further comprises a resistor coupled between the first and second output nodes, and a current source coupled between the second output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 51

The control circuit defined in claim 41 wherein the waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node, the second periodic waveform generator providing a second periodic waveform at a second waveform output node, the third output node of the signal generator circuitry coupled to the first waveform output node, and the fourth output node of the signal generator circuitry coupled to the second waveform output node.

Claim 52

The control circuit defined in claim 41 wherein the periodic waveform is a sawtooth waveform.

Claim 53

The control circuit defined in claim 41 wherein the periodic waveform is a triangular waveform.

Claim 54

The control circuit defined in claim 41 wherein the control circuit further comprises first and second multiplexer circuits, the first multiplexer circuit coupled between the first input of the logic circuitry and the outputs of each of the first and second comparators, the second multiplexer circuit coupled between the second input of the logic circuitry and the outputs of each of the first and second comparators.

Claim 55

The control circuit defined in claim 41 wherein the control circuit further comprises: an amplifier circuit having first and second inputs, and an output coupled to the input node of the signal generator circuitry; a first resistor coupled between the output node of the switching regulator circuit and the first input of the amplifier circuit; and a second resistor coupled between the first input of the amplifier circuit and GROUND.

Claim 56

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a first diode with an anode coupled to GROUND and a cathode coupled to the first terminal of the inductor, a second switch coupled between a second terminal of the inductor and GROUND, and a second diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, and second outputs coupled to the first and second switches, respectively.

Claim 57

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a first diode with an anode coupled to GROUND and a cathode coupled to the first terminal of the inductor, a second switch coupled between a second terminal of the inductor and GROUND, and a second diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, and second outputs coupled to the first and second switches, respectively.

Claim 58

The control circuit defined in claim 51 wherein a direct current offset is created between the third and fourth output nodes of the signal generator circuitry.

Claim 59

The control circuit defined in claim 52 wherein the signal generator circuitry further comprises a resistor coupled between the third and fourth output nodes, and a current source coupled between the fourth output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 60

The control circuit defined in claim 51 wherein a direct current offset is created between the first and second output nodes of the signal generator circuitry.

Claim 61

The control circuit defined in claim 54 wherein the signal generator circuitry further comprises a resistor coupled between the first and second output nodes, and a current source coupled between the second output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 62

The control circuit defined in claim 51 wherein the waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node, the second periodic waveform generator providing a second periodic waveform at a second waveform output node, the third output node of the signal generator circuitry coupled to the first waveform output node, and the fourth output node of the signal generator circuitry coupled to the second waveform output node.

Claim 63

The control circuit defined in claim 51 wherein the periodic waveform is a sawtooth waveform.

Claim 64

The control circuit defined in claim 51 wherein the periodic waveform is a triangular waveform.

Claim 65

The control circuit defined in claim 51 wherein the control circuit further comprises first and second multiplexer circuits, the first multiplexer circuit coupled between the first input of the logic circuitry and the outputs of each of the first and second comparators, the second multiplexer circuit coupled between the second input of the logic circuitry and the outputs of each of the first and second comparators.

Claim 66

The control circuit defined in claim 51 wherein the control circuit further comprises: an amplifier circuit having first and second inputs, and an output coupled to the input node of the signal generator circuitry; a first resistor coupled between the output node of the switching regulator circuit and the first input of the amplifier circuit; and a second resistor coupled between the first input of the amplifier circuit and GROUND.

Claim 67

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a second switch coupled between the first terminal of the inductor and GROUND, a third switch coupled between a second terminal of the inductor and GROUND, and a diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, and third outputs coupled to the first, second, and third switches, respectively, wherein the first switch is OFF when the second switch is ON, and the second switch is OFF when the first switch is ON.

Claim 68

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a second switch coupled between the first terminal of the inductor and GROUND, a third switch coupled between a second terminal of the inductor and GROUND, and a diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, and third outputs coupled to the first, second, and third switches, respectively, wherein the first switch is OFF when the second switch is ON, and the second switch is OFF when the first switch is ON.

Claim 69

The control circuit defined in claim 61 wherein a direct current offset is created between the third and fourth output nodes of the signal generator circuitry.

Claim 70

The control circuit defined in claim 62 wherein the signal generator circuitry further comprises a resistor coupled between the third and fourth output nodes, and a current source coupled between the fourth output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 71

The control circuit defined in claim 61 wherein a direct current offset is created between the first and second output nodes of the signal generator circuitry.

Claim 72

The control circuit defined in claim 64 wherein the signal generator circuitry further comprises a resistor coupled between the first and second output nodes, and a current source coupled between the second output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 73

The control circuit defined in claim 61 wherein the waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node, the second periodic waveform generator providing a second periodic waveform at a second waveform output node, the third output node of the signal generator circuitry coupled to the first waveform output node, and the fourth output node of the signal generator circuitry coupled to the second waveform output node.

Claim 74

The control circuit defined in claim 61 wherein the periodic waveform is a sawtooth waveform.

Claim 75

The control circuit defined in claim 61 wherein the periodic waveform is a triangular waveform.

Claim 76

The control circuit defined in claim 61 wherein the control circuit further comprises first and second multiplexer circuits, the first multiplexer circuit coupled between the first input of the logic circuitry and the outputs of each of the first and second comparators, the second multiplexer circuit coupled between the second input of the logic circuitry and the outputs of each of the first and second comparators.

Claim 77

The control circuit defined in claim 61 wherein the control circuit further comprises: an amplifier circuit having first and second inputs, and an output coupled to the input node of the signal generator circuitry; a first resistor coupled between the output node of the switching regulator circuit and the first input of the amplifier circuit; and a second resistor coupled between the first input of the amplifier circuit and GROUND.

Claim 78

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a diode with an anode coupled to GROUND and a cathode coupled to the first terminal of the inductor, a second switch coupled between a second terminal of the inductor and GROUND, and a third switch coupled between the second terminal of the inductor and the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, and third outputs coupled to the first, second, and third switches, respectively, wherein the third switch is OFF when the second switch is ON, and the second switch is OFF when the third switch is ON.

Claim 79

A control circuit for controlling a buck-boost switching regulator circuit for supplying a regulated output voltage at an output node, the buck-boost switching regulator comprising an inductor, a first switch coupled between an input voltage and a first terminal of the inductor, a diode with an anode coupled to GROUND and a cathode coupled to the first terminal of the inductor, a second switch coupled between a second terminal of the inductor and GROUND, and a third switch coupled between the second terminal of the inductor and the output node, the control circuit comprising: signal generator circuitry comprising an input node coupled to the output node of the switching regulator circuit, a waveform generator providing a periodic waveform at an waveform output node, and first, second, third, and fourth output nodes, the first and second output nodes coupled to the input node of the signal generator circuitry, the third and fourth output nodes coupled to the waveform output node of the waveform generator; a first comparator circuit comprising a first and second inputs coupled to the first and third output nodes, respectively, of the signal generator circuitry; a second comparator circuit comprising a first and second inputs coupled to the second and fourth output nodes, respectively, of the signal generator circuitry; and logic circuitry comprising logic gates, the logic circuitry having a first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and first, second, and third outputs coupled to the first, second, and third switches, respectively, wherein the third switch is OFF when the second switch is ON, and the second switch is OFF when the third switch is ON.

Claim 80

The control circuit defined in claim 71 wherein a direct current offset is created between the third and fourth output nodes of the signal generator circuitry.

Claim 81

The control circuit defined in claim 72 wherein the signal generator circuitry further comprises a resistor coupled between the third and fourth output nodes, and a current source coupled between the fourth output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 82

The control circuit defined in claim 71 wherein a direct current offset is created between the first and second output nodes of the signal generator circuitry.

Claim 83

The control circuit defined in claim 74 wherein the signal generator circuitry further comprises a resistor coupled between the first and second output nodes, and a current source coupled between the second output node and GROUND, the resistor and the current source creating the direct current offset.

Claim 84

The control circuit defined in claim 71 wherein the waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node, the second periodic waveform generator providing a second periodic waveform at a second waveform output node, the third output node of the signal generator circuitry coupled to the first waveform output node, and the fourth output node of the signal generator circuitry coupled to the second waveform output node.

Claim 85

The control circuit defined in claim 71 wherein the periodic waveform is a sawtooth waveform.

Claim 86

The control circuit defined in claim 71 wherein the periodic waveform is a triangular waveform.

Claim 87

The control circuit defined in claim 71 wherein the control circuit further comprises first and second multiplexer circuits, the first multiplexer circuit coupled between the first input of the logic circuitry and the outputs of each of the first and second comparators, the second multiplexer circuit coupled between the second input of the logic circuitry and the outputs of each of the first and second comparators.

Claim 88

The control circuit defined in claim 71 wherein the control circuit further comprises: an amplifier circuit having first and second inputs, and an output coupled to the input node of the signal generator circuitry; a first resistor coupled between the output node of the switching regulator circuit and the first input of the amplifier circuit; and a second resistor coupled between the first input of the amplifier circuit and GROUND.