Abstract The as-deposited thickness of at least one of the oxide layers of a composite ONO dielectric film between a floating gate and a control gate of a non-volatile semiconductor device is deposited to a sufficient thickness such that, after the top oxide layer is cleaned, the control gate is spaced apart from the floating gate a distance corresponding to at least a minimum design data retention. Deposition is facilitated by forming one or more oxide layers at a thickness greater than the design rule by employing a relatively high dielectric constant material for the oxide layer or layers, such as aluminum oxide, titanium oxide or tantalum oxide. In this way, the capacitance of the ONO film between the floating gate and the control gate is maintained per design rule, avoiding a change in operating voltage. Embodiments include depositing a relatively thick top oxide layer to enable thorough cleaning without adversely reducing the total thickness of the ONO stack and, hence, achieving design data retention.
A semiconductor device comprising: a tunnel oxide layer on a channel region of a semiconductor substrate; a floating gate on the tunnel oxide layer; a control gate formed above the floating gate and spaced apart from the floating gate at least a predetermined distance; and a composite dielectric layer between the control gate and the floating gate, the dielectric layer comprising: a first oxide layer on the floating gate, the first oxide layer having a first thickness; a nitride layer on the first oxide layer, the nitride layer having a second thickness; and a second oxide layer having a dielectric constant about equal to or greater than 10 and having a third thickness; wherein the sum of the first, second and third thicknesses corresponds to at least a minimum design data retention; and wherein the first and second oxide layers and the nitride layer have a combined capacitance corresponding to the design rule of the semiconductor device.
Claim 2
Dependent Claim
157 words
A semiconductor device comprising: a tunnel oxide layer on a channel region of a semiconductor substrate; a floating gate on the tunnel oxide layer; a control gate formed above the floating gate and spaced apart from the floating gate at least a predetermined distance; and a composite dielectric layer between the control gate and the floating gate, the dielectric layer comprising: a first oxide layer on the floating gate, the first oxide layer having a first thickness; a nitride layer on the first oxide layer, the nitride layer having a second thickness; and a second oxide layer having a dielectric constant about equal to or greater than 10 and having a third thickness; wherein the sum of the first, second and third thicknesses corresponds to at least a minimum design data retention; and wherein the first and second oxide layers and the nitride layer have a combined capacitance corresponding to the design rule of the semiconductor device.
Claim 3
Dependent Claim
43 words
The semiconductor device according to claim 1, wherein the combined first, second and third thicknesses exceed the design rule of the semiconductor device; and the first and/or second oxide layer comprises an oxide having a dielectric constant greater than that of silicon dioxide.
Claim 4
Dependent Claim
28 words
The semiconductor device according to claim 2, wherein the first oxide layer comprises silicon dioxide and the second oxide layer comprises aluminum oxide, titanium oxide or tantalum oxide.
Claim 5
Dependent Claim
17 words
The semiconductor device according to claim 3, wherein the third thickness is greater than about 55 Å.
Claim 6
Dependent Claim
30 words
The semiconductor device according to claim 1, wherein the first and/or second oxide layers each comprise aluminum oxide, titanium oxide or tantalum oxide, and the nitride layer comprises silicon nitride.