Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Claim 1

A method for making polysilicon landing plugs and metal landing plugs with electrical interconnections for contacts on semiconductor integrated circuits comprising the steps of: providing a semiconductor substrate having device areas of a first type and device areas of a second type, and having devices with N - doped contacts in said device areas of a first type, and having N + and P + doped contacts in said device areas of a second type; depositing a conformal first etch-stop layer and partially etching back to form sidewall spacers on said devices and to protect said device areas; depositing an insulating layer which is planarized; etching first contact openings in said insulating layer to said first etch-stop layer over said N - doped contacts in said device areas of a first type, and selectively removing said first etch-stop layer in said first contact openings to expose said N - doped contacts, wherein said first openings are self-aligned to said devices; depositing an N + doped polysilicon layer on said substrate and contacting said N - doped contacts; etching second openings in said polysilicon layer and said insulating layer to said first etch-stop layer over said N + and said P + contact regions in said device areas of a second type; selectively etching said first etch-stop layer in said second openings to expose said N + and said P + contact regions; depositing an electrically conducting barrier layer; depositing a metal layer over said barrier layer sufficiently thick to fill said first and said second openings, and to provide an essentially planar surface; depositing a second etch-stop layer; patterning said second etch-stop layer, said metal layer, said barrier layer, and said polysilicon layer to form interconnecting lines, and concurrently to form N + doped said polysilicon landing plugs in said device areas of a first type, and forming said metal landing plugs to said N + and said P + contact regions in said device areas of a second type, and completing said polysilicon landing plugs and said metal landing plugs and said electrical interconnections.

Claim 2

A method for making polysilicon landing plugs and metal landing plugs with electrical interconnections for contacts on semiconductor integrated circuits comprising the steps of: providing a semiconductor substrate having device areas of a first type and device areas of a second type, and having devices with N - doped contacts in said device areas of a first type, and having N + and P + doped contacts in said device areas of a second type; depositing a conformal first etch-stop layer and partially etching back to form sidewall spacers on said devices and to protect said device areas; depositing an insulating layer which is planarized; etching first contact openings in said insulating layer to said first etch-stop layer over said N - doped contacts in said device areas of a first type, and selectively removing said first etch-stop layer in said first contact openings to expose said N - doped contacts, wherein said first openings are self-aligned to said devices; depositing an N + doped polysilicon layer on said substrate and contacting said N - doped contacts; etching second openings in said polysilicon layer and said insulating layer to said first etch-stop layer over said N + and said P + contact regions in said device areas of a second type; selectively etching said first etch-stop layer in said second openings to expose said N + and said P + contact regions; depositing an electrically conducting barrier layer; depositing a metal layer over said barrier layer sufficiently thick to fill said first and said second openings, and to provide an essentially planar surface; depositing a second etch-stop layer; patterning said second etch-stop layer, said metal layer, said barrier layer, and said polysilicon layer to form interconnecting lines, and concurrently to form N + doped said polysilicon landing plugs in said device areas of a first type, and forming said metal landing plugs to said N + and said P + contact regions in said device areas of a second type, and completing said polysilicon landing plugs and said metal landing plugs and said electrical interconnections.

Claim 12

A method for making polysilicon landing plugs and metal landing plugs with electrical interconnections for contacts on semiconductor integrated circuits comprising the steps of: providing a semiconductor substrate having first device areas and second device areas surrounded and electrically isolated from each other by field oxide areas; forming a gate oxide on said device areas; forming a polycide layer on said substrate; depositing a cap insulating layer composed of silicon oxide/silicon nitride on said polycide layer; patterning said cap insulating layer and said polycide layer to form field effect transistor (FET) gate electrodes; forming N - doped source/drain contact areas by ion implantation in said first device areas; depositing a conformal first silicon nitride layer and partially etching back to form sidewall spacers on said gate electrodes and to protect said device areas; using ion implant block-out masks to form N + and P + contact regions in said second device areas; depositing a first insulating layer which is planarized; using a first photoresist mask and anisotropically and selectively etching first contact openings in said first insulating layer to said first silicon nitride layer in said first device areas, and selectively removing said first silicon nitride layer in said first contact openings; removing said first photoresist mask; depositing an N + doped polysilicon layer on said substrate and contacting said N - source/drain contact areas; using a second photoresist mask and anisotropically and selectively etching second openings in said polysilicon layer and said first insulating layer to said gate electrodes and to said first silicon nitride layer on said substrate to said N + and said P + contact regions in said second device areas; selectively etching said first silicon nitride layer in said second openings; depositing an electrically conducting first barrier layer; depositing a first metal layer over said first barrier layer sufficiently thick to fill said first and said second openings, and to provide an essentially planar surface; depositing a second silicon nitride layer; patterning said second silicon nitride layer, said first metal layer, said first barrier layer, and said polysilicon layer to form interconnecting lines and concurrently to form N + doped said polysilicon landing plugs in said first device areas and forming said metal landing plugs to said N + and said P + contact regions in said second device areas; depositing a third silicon nitride layer and etching back to form silicon nitride sidewall spacers on said interconnecting lines; depositing and planarizing a second insulating layer; forming via holes in said second insulating layer to said polysilicon landing plugs, to said metal landing plugs, and to said interconnecting lines; depositing an electrically conducting second barrier layer and a second metal layer and etching back to form metal plugs in said via holes to said polysilicon landing plugs and said metal landing plugs; depositing and patterning a conducting third metal layer to complete said integrated circuits up to a first level of metal interconnections.

Claim 13

A method for making polysilicon landing plugs and metal landing plugs with electrical interconnections for contacts on semiconductor integrated circuits comprising the steps of: providing a semiconductor substrate having first device areas and second device areas surrounded and electrically isolated from each other by field oxide areas; forming a gate oxide on said device areas; forming a polycide layer on said substrate; depositing a cap insulating layer composed of silicon oxide/silicon nitride on said polycide layer; patterning said cap insulating layer and said polycide layer to form field effect transistor (FET) gate electrodes; forming N - doped source/drain contact areas by ion implantation in said first device areas; depositing a conformal first silicon nitride layer and partially etching back to form sidewall spacers on said gate electrodes and to protect said device areas; using ion implant block-out masks to form N + and P + contact regions in said second device areas; depositing a first insulating layer which is planarized; using a first photoresist mask and anisotropically and selectively etching first contact openings in said first insulating layer to said first silicon nitride layer in said first device areas, and selectively removing said first silicon nitride layer in said first contact openings; removing said first photoresist mask; depositing an N + doped polysilicon layer on said substrate and contacting said N - source/drain contact areas; using a second photoresist mask and anisotropically and selectively etching second openings in said polysilicon layer and said first insulating layer to said gate electrodes and to said first silicon nitride layer on said substrate to said N + and said P + contact regions in said second device areas; selectively etching said first silicon nitride layer in said second openings; depositing an electrically conducting first barrier layer; depositing a first metal layer over said first barrier layer sufficiently thick to fill said first and said second openings, and to provide an essentially planar surface; depositing a second silicon nitride layer; patterning said second silicon nitride layer, said first metal layer, said first barrier layer, and said polysilicon layer to form interconnecting lines and concurrently to form N + doped said polysilicon landing plugs in said first device areas and forming said metal landing plugs to said N + and said P + contact regions in said second device areas; depositing a third silicon nitride layer and etching back to form silicon nitride sidewall spacers on said interconnecting lines; depositing and planarizing a second insulating layer; forming via holes in said second insulating layer to said polysilicon landing plugs, to said metal landing plugs, and to said interconnecting lines; depositing an electrically conducting second barrier layer and a second metal layer and etching back to form metal plugs in said via holes to said polysilicon landing plugs and said metal landing plugs; depositing and patterning a conducting third metal layer to complete said integrated circuits up to a first level of metal interconnections.