US6154819A
Expired / Lapsed
US
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Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks
Assignee: Intel Corp
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Filing: 1998-05-11
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Granted: 2000-11-28
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Expires: 2018-05-11
Abstract
Abstract An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.
Inventors
- 👤 Robert E. Larsen
- 👤 Peter Hazen
- 👤 Sanjay S. Talreja
- 👤 Sandeep Guliani
- 👤 Robert N. Hasbun
- 👤 Collin Ong
- 👤 Terry D. West
- 👤 Charles Brown
- 👤 Terry L. Kendall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:56
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
155 words
An apparatus comprising: a non-volatile memory array including a plurality of blocks, one or more blocks of said plurality of blocks being capable of being placed in a locked state or an unlocked state; a volatile lock register coupled to a block of said one or more blocks; a volatile lock-down register coupled to said block of said one or more blocks; a hardware override line coupled to said lock register and said lock-down register, said hardware override line temporarily disabling said lock-down register when said hardware override line transmits a signal set to a first logic state; a block lock control line coupled to said lock register and transmitting a lock control signal to said lock resister; a block lock-down control line coupled to said lock-down register and transmitting a lock-down control signal to said lock-down register; and a block select control line coupled to each of said lock register and said lock-down register.
Claim 2
Independent Claim
155 words
An apparatus comprising: a non-volatile memory array including a plurality of blocks, one or more blocks of said plurality of blocks being capable of being placed in a locked state or an unlocked state; a volatile lock register coupled to a block of said one or more blocks; a volatile lock-down register coupled to said block of said one or more blocks; a hardware override line coupled to said lock register and said lock-down register, said hardware override line temporarily disabling said lock-down register when said hardware override line transmits a signal set to a first logic state; a block lock control line coupled to said lock register and transmitting a lock control signal to said lock resister; a block lock-down control line coupled to said lock-down register and transmitting a lock-down control signal to said lock-down register; and a block select control line coupled to each of said lock register and said lock-down register.
Claim 3
Dependent Claim
50 words
The apparatus of claim 1 further comprising a logic circuit coupled to an output of said lock register and an output of said lock down register, said logic circuit transmitting a lock status control signal to said block, and wherein said hardware override line is coupled to said logic circuit.
Claim 4
Dependent Claim
84 words
The apparatus of claim 2 wherein, said lock control signal programs said lock register to a first lock state or a second lock state, said first lock state preventing said block from being programmed or erased; and said lock-down control signal programs said lock-down register to a first lock-down state or a second lock-down state, said first lock-down state preventing said block from being programmed or erased and further preventing programming of said lock register to allow said block to be programmed or erased.
Claim 5
Dependent Claim
50 words
The apparatus of claim 3 wherein said hardware override line transmits a write protect signal having a first write protect state or a second write protect state, said first write protect state preventing said lock-down register from preventing said lock register to allow said block to be programmed or erased.
Claim 6
Dependent Claim
31 words
The apparatus of claim 4 wherein said non-volatile memory array is a flash memory and said lock register and said lock-down register are both embodied in static random access memory circuits.
Claim 7
Independent Claim
252 words
An apparatus comprising: a non-volatile memory array including a plurality of blocks, one or more blocks of said plurality of blocks being capable of being placed in a locked state or an unlocked state; a set of volatile lock registers, each lock register of said set of lock registers coupled to a corresponding block of said one or more blocks, and operable to prevent corresponding blocks from being modified; a set of volatile lock-down registers, each lock-down register of said set of lock-down registers being associated with a lock register of said set of volatile lock registers and operable to prevent said corresponding blocks from being modified, and further operable to prevent said set of lock registers to be programmed to allow said corresponding blocks to modified; a hardware override line coupled to said set of lock registers and said set of lock-down registers, said hardware override line operable to temporarily disable operation of said set of lock-down registers; and a command buffer coupled to said set of lock registers and said set of lock-down registers, said command buffer operable to transmit a two-cycle command to each register of both said set of lock registers and said set of lock-down registers, wherein the first cycle comprises a command specifying whether a lock configuration of said non-volatile memory array is to be changed, and the second cycle comprises a command specifying whether a block of said memory array is to be placed in a lock state, an unlocked state, or a locked-down state.
Claim 8
Independent Claim
252 words
An apparatus comprising: a non-volatile memory array including a plurality of blocks, one or more blocks of said plurality of blocks being capable of being placed in a locked state or an unlocked state; a set of volatile lock registers, each lock register of said set of lock registers coupled to a corresponding block of said one or more blocks, and operable to prevent corresponding blocks from being modified; a set of volatile lock-down registers, each lock-down register of said set of lock-down registers being associated with a lock register of said set of volatile lock registers and operable to prevent said corresponding blocks from being modified, and further operable to prevent said set of lock registers to be programmed to allow said corresponding blocks to modified; a hardware override line coupled to said set of lock registers and said set of lock-down registers, said hardware override line operable to temporarily disable operation of said set of lock-down registers; and a command buffer coupled to said set of lock registers and said set of lock-down registers, said command buffer operable to transmit a two-cycle command to each register of both said set of lock registers and said set of lock-down registers, wherein the first cycle comprises a command specifying whether a lock configuration of said non-volatile memory array is to be changed, and the second cycle comprises a command specifying whether a block of said memory array is to be placed in a lock state, an unlocked state, or a locked-down state.
Claim 9
Dependent Claim
64 words
The apparatus of claim 6 wherein said locked state corresponds to a lock register of said set of lock registers being programmed to a first logic state, said unlocked state corresponds to said lock register being programmed to a second logic state, and said locked-down state corresponds to a lock-down register of said set of lock-down registers being programmed to a first logic state.
Claim 10
Dependent Claim
26 words
The apparatus of claim 7 wherein said lock-down state prevents programming of lock registers to allow corresponding blocks of said non-volatile memory array to be modified.
Claim 11
Dependent Claim
47 words
The apparatus of claim 8 wherein said hardware override line is operable to temporarily override said lock-down state to thereby allow programming of said lock registers to allow said corresponding blocks of said non-volatile memory to be modified regardless of the lock-down state of corresponding lock-down registers.
Claim 12
Dependent Claim
35 words
The apparatus of claim 9 wherein said non-volatile memory array is a flash memory and said first set of lock registers and said set of lock-down registers are embodied in static random access memory circuits.
Claim 13
Dependent Claim
28 words
The apparatus of claim 10 wherein said lock-down registers are capable of being set to a lock-down only once during a period in which said apparatus is powered-up.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |