US6151697A
Expired / Lapsed
US
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Signal processing apparatus and method
Assignee: Bang and Olufsen AS
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Filing: 1997-10-30
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Granted: 2000-11-21
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Expires: 2017-10-30
Abstract
Abstract An apparatus and method of processing signals is provided wherein an input signal has components representing aspects of a physical entity which are in a known state and other components which are unknown. The apparatus and method processes the signal in accordance with stored data representing rules which indicate which combinations of the components are possible. Rules are identified which involve the known components and all of the combinations consistent with the known states are identified. If all of these combinations have the same value for a particular component, the component is determined to have that value in the output signal. The rules are stored as binary representations of the possible combinations, and the components of the input and output signals may represent two allowable states, tautology (undefined state) and inconsistency (inallowable state).
Inventors
- 👤 Gert Lykke Moeller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 04:19
CPC Classifications
G; G06; G06N; G06N5/00; G06N5/02; G06N5/022; G06N5/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
An information processing apparatus for processing an input signal to determine an output signal for a system having a plurality of system variables, the input signal having a plurality of variables including at least one variable with an unknown value defining an unbounded variable and at least one variable with a known value defining a bounded variable, the unbounded variable defining uncertainty for the input signal, the variables in the system constrained by a plurality of predetermined rules, the rules including predetermined combinations of a plurality of system variables, the information processing system comprising: an addressable memory having stored therein a binary representation of the rules constraining the variables in the system; proposition storage memory having stored therein a binary representation indicating which rules define a relationship for a variable; scanning means for receiving the input signal, and for scanning the proposition storage memory to identify all rules which define a relationship for a variable; logic means for addressing the respective identified rules in the addressable memory and determining from the input signal and the rules all of the bounded system variables for a given input signal by determining which variables have the same bounded value in all of the identified rules.
Claim 2
Dependent Claim
202 words
An information processing apparatus for processing an input signal to determine an output signal for a system having a plurality of system variables, the input signal having a plurality of variables including at least one variable with an unknown value defining an unbounded variable and at least one variable with a known value defining a bounded variable, the unbounded variable defining uncertainty for the input signal, the variables in the system constrained by a plurality of predetermined rules, the rules including predetermined combinations of a plurality of system variables, the information processing system comprising: an addressable memory having stored therein a binary representation of the rules constraining the variables in the system; proposition storage memory having stored therein a binary representation indicating which rules define a relationship for a variable; scanning means for receiving the input signal, and for scanning the proposition storage memory to identify all rules which define a relationship for a variable; logic means for addressing the respective identified rules in the addressable memory and determining from the input signal and the rules all of the bounded system variables for a given input signal by determining which variables have the same bounded value in all of the identified rules.
Claim 3
Dependent Claim
15 words
The information processing apparatus as claimed in claim 1 binary representation of the rules size.
Claim 4
Dependent Claim
37 words
The information processing apparatus as claimed in claim 2 wherein the logic means further comprises means for determining whether the values of the variables in the input signal contradict the constraints for the variables in the rules.
Claim 5
Dependent Claim
17 words
The information processing apparatus as claimed in claim 2 wherein the logic means comprises a computer processor.
Claim 6
Dependent Claim
24 words
The information processing apparatus as claimed in claim 1 wherein the binary representation of the rules comprises a truth table representation of the rules.
Claim 7
Dependent Claim
42 words
The information processing apparatus as claimed in claim 1 wherein the binary representation of the rules includes a binary representation of the combinations of the system variables in positive index form thereby representing the combination allowed by the constraints of the rules.
Claim 8
Dependent Claim
28 words
The information processing apparatus as claimed in claim 1 wherein the binary representation of the rules includes a binary representation of the unallowed combinations of the system variables.
Claim 9
Dependent Claim
54 words
The information processing apparatus as claimed in claim 1 further comprising means for storing a binary representation of the input signal and wherein the logic means includes means for changing unbounded variables to their determined bounded value in the stored signal when the logic means determines the bounded value of an initially unbounded variable.
Claim 10
Dependent Claim
38 words
The information processing apparatus as claimed in claim 8 wherein the logic means further comprises means for determining whether the values of the variable in the input signal result in a contradiction of the constraints of the rules.
Claim 11
Dependent Claim
24 words
The information processing apparatus as claimed in claim 9 further comprising means for indicating which rule resulted in a contradiction if a contradiction occurs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |