US6150847A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device and method for generating a variable duty cycle clock
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1999-07-21
•
Granted: 2000-11-21
•
Expires: 2019-07-21
Abstract
Abstract A device for generating a variable duty cycle clock is provided, which includes a frequency divider, a plurality of first M-stage delay elements, a plurality of second M-stage delay elements, a selector and a logic gate, where M is an integer. The frequency divider divides an input clock to obtain a divided clock. The first M-stage delay elements, which are connected in series, sequentially delay the divided clock for a first delay time to obtain M first delay clocks. The second M-stage delay elements, which are also connected in series and are corresponding to the first M-stage delay elements, sequentially delay the divided clock for a second delay time to obtain M second delay clocks. The second delay time is in a variable proportion to the first delay time. The selector compares the divided clock and each of the M first delay clocks to obtain M state signals. The M state signals are used to select a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks. The logic gate XORs the divided clock and the second selected clock to obtain the variable duty cycle clock.
Inventors
- 👤 Jr-Houng Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:21
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
A device for generating a variable duty cycle clock, comprising: a frequency divider for dividing an input clock to obtain a divided clock; a plurality of first delay elements connected in series, for sequentially delaying the divided clock for a first delay time to obtain a plurality of first delay clocks; a plurality of second delay elements connected in series and corresponding to the first delay elements, for sequentially delaying the divided clock for a second delay time to obtain a plurality of second delay clocks, wherein the second delay time is in a variable proportion to the first delay time; a selector for comparing the divided clock and the first delay clocks to obtain a plurality of state signals for selecting a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks; and a logic circuit for XORing the divided clock and the second selected clock to obtain the variable duty cycle clock.
Claim 2
Independent Claim
176 words
A device for generating a variable duty cycle clock, comprising: a frequency divider for dividing an input clock to obtain a divided clock; a plurality of first delay elements connected in series, for sequentially delaying the divided clock for a first delay time to obtain a plurality of first delay clocks; a plurality of second delay elements connected in series and corresponding to the first delay elements, for sequentially delaying the divided clock for a second delay time to obtain a plurality of second delay clocks, wherein the second delay time is in a variable proportion to the first delay time; a selector for comparing the divided clock and the first delay clocks to obtain a plurality of state signals for selecting a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks; and a logic circuit for XORing the divided clock and the second selected clock to obtain the variable duty cycle clock.
Claim 3
Dependent Claim
59 words
The device for generating the variable duty cycle clock as claimed in claim 1, wherein the frequency divider is constructed with a D-type flip flop having a clock terminal (CLK) receiving the input clock, an inverse output terminal (Qn), a data terminal (D) connected to the inverse output terminal (Qn), and an output terminal (Q) outputting the divided clock.
Claim 4
Dependent Claim
47 words
The device for generating the variable duty cycle clock as claimed in claim 1, wherein the first delay elements are constructed with a delay line having a plurality of first line segments connected in series, and each of the first line segments has the first delay time.
Claim 5
Dependent Claim
47 words
The device for generating the variable duty cycle clock as claimed in claim 1, wherein the second delay elements are constructed with a delay line having a plurality of second line segments connected in series, and each of the second line segments has the second delay time.
Claim 6
Dependent Claim
90 words
The device for generating a variable duty cycle clock as claimed in claim 1, further comprising: a plurality of AND gates for ANDing the divided clock and the first delay clocks to obtain a plurality of shrunk clocks; a plurality of latches for latching the shrunk clocks to obtain a plurality of latch signals; a plurality of XOR gates for XORing adjacent latch signals to obtain state signals corresponding to the second delay elements; and a plurality of switches for selecting the second selected clock according to the state signals.
Claim 7
Dependent Claim
36 words
The device for generating the variable duty cycle clock as claimed in claim 5, wherein each of the switches is constructed with a transmission gate having a control terminal connected to one of the state signals.
Claim 8
Independent Claim
149 words
A method for generating a variable duty cycle clock, comprising: providing an input clock; frequency dividing the input clock to obtain a divided clock; sequentially delaying the divided clock for a first delay time to obtain a plurality of first delay clocks; sequentially delaying the divided clock for a second delay time to obtain a plurality of second delay clocks corresponding to the first delay clocks, wherein the second delay time is in a variable proportion to the first delay time; comparing the divided clock and the first delay clocks to obtain a plurality of state signals for selecting a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks; and XORing the divided clock and the second selected clock to generate the variable duty cycle clock.
Claim 9
Independent Claim
149 words
A method for generating a variable duty cycle clock, comprising: providing an input clock; frequency dividing the input clock to obtain a divided clock; sequentially delaying the divided clock for a first delay time to obtain a plurality of first delay clocks; sequentially delaying the divided clock for a second delay time to obtain a plurality of second delay clocks corresponding to the first delay clocks, wherein the second delay time is in a variable proportion to the first delay time; comparing the divided clock and the first delay clocks to obtain a plurality of state signals for selecting a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks; and XORing the divided clock and the second selected clock to generate the variable duty cycle clock.
Claim 10
Dependent Claim
59 words
The method for generating the variable duty cycle clock as claimed in claim 7, wherein the divided clock is generated by a D-type flip flop having a clock terminal (CLK) receiving the input clock, an inverse output terminal (Qn), a data terminal (D) connected to the inverse output terminal (Qn), and an output terminal (Q) outputting the divided clock.
Claim 11
Dependent Claim
47 words
The method for generating the variable duty cycle clock as claimed in claim 7, wherein the first delay clocks are generated by a delay line having a plurality of first line segments connected in series, and each of the first line segments has the first delay time.
Claim 12
Dependent Claim
47 words
The method for generating the variable duty cycle clock as claimed in claim 7, wherein the second delay clocks are generated by a delay line having a plurality of second line segments connected in series, and each of the second line segments has the second delay time.
Claim 13
Dependent Claim
56 words
The method for generating a variable duty cycle clock as claimed in claim 7, further comprising the steps of: ANDing the divided clock and the first delay clocks to obtain a plurality of shrunk clocks; latching the shrunk clocks to obtain a plurality of latch signals; and XORing adjacent latch signals to obtain the state signals.
Claim 14
Dependent Claim
48 words
The method for generating the variable duty cycle clock as claimed in claim 7, wherein the second selected clock is selected by a plurality of switches corresponding to the second delay clocks, and each of the switches has a control terminal connected to one of the state signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |