US6148038A — Circuit for detecting and decoding phase encoded …

Claim 1

Independent Claim 88 words

A decoder apparatus for decoding a phase-encoded digital data signal comprising: a first delay line receiving the phase-encoded digital data signal; a second delay line operating at a different rate than the first delay line and receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.

Claim 2

Dependent Claim 88 words

A decoder apparatus for decoding a phase-encoded digital data signal comprising: a first delay line receiving the phase-encoded digital data signal; a second delay line operating at a different rate than the first delay line and receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.

Claim 3

Dependent Claim 31 words

The decoder apparatus according to claim 1, further comprising: a data recovery circuit, coupled to the decoder logic circuit, for receiving and holding the value extracted by the decoder logic circuit.

Claim 4

Dependent Claim 34 words

The decoder apparatus according to claim 1, further comprising: a synchronizing circuit coupled to the inputs of the first and second delay lines to produce the phase-encoded digital data signal from a transmitted signal.

Claim 5

Dependent Claim 26 words

The decoder apparatus according to claim 3, wherein the synchronizing circuit includes jitter circuitry configured to eliminate jitter present in the received phase-encoded digital data signal.

Claim 6

Dependent Claim 21 words

The decoder apparatus according to claim 3, wherein the synchronizing circuit is one of a phase-locked loop and a delay-locked loop.

Claim 7

Dependent Claim 33 words

The decoder apparatus according to claim 1, wherein the decoder logic circuit includes circuitry configured to sample data at an edge of the received phase-encoded digital data signal in the first delay line.

Claim 8

Dependent Claim 22 words

The decoder apparatus according to claim 1, wherein the decoder logic circuit includes a plurality of registers for holding the sampled data.

Claim 9

Dependent Claim 38 words

The decoder apparatus according to claim 7, wherein the decoder logic circuit further includes encoding circuitry to encode a state of the registers as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 10

Dependent Claim 23 words

The decoder apparatus according to claim 8, wherein the encoding circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 11

Dependent Claim 37 words

The decoder apparatus according to claim 1, wherein the first delay line includes a first number of delay gates coupled in series; and the second delay line includes a first number of delay gates coupled in series.

Claim 12

Dependent Claim 45 words

The decoder apparatus according to claim 10, wherein the delay gates of the first delay line each impart a first delay and the delay gates of the second delay line each impart a second delay, and where the first delay is twice the second delay.

Claim 13

Dependent Claim 21 words

The decoder apparatus according to claim 11, further comprising delay control circuitry to adjust the first delay and the second delay.

Claim 14

Dependent Claim 31 words

The decoder apparatus according to claim 11, further comprising a synchronizing circuit configured to align the received phase-encoded digital data signal at the inputs of the first and second delay lines.

Claim 15

Dependent Claim 32 words

The decoder apparatus according to claim 7, wherein the plurality of registers have a clock input coupled to the first delay line and a data input coupled to the second delay line.

Claim 16

Dependent Claim 37 words

The decoder apparatus according to claim 14, wherein the first delay line includes a first number of delay gates coupled in series; and the second delay line includes a first number of delay gates coupled in series.

Claim 17

Dependent Claim 81 words

The decoder apparatus according to claim 15, wherein each of the registers corresponds to a different one of the delay gates in the first and second delay lines at the same relative position in the series of delay gates; and wherein the clock input of each of the registers connects to the input of the corresponding delay gate in the first delay line and the data input connects to the input of the corresponding delay gate in the second delay line.

Claim 18

Dependent Claim 40 words

The decoder apparatus according to claim 16, wherein a first register of the plurality of registers of the decoder logic circuit includes circuitry configured to latch to the first register an error condition of the received phase-encoded digital data signal.

Claim 19

Dependent Claim 43 words

The decoder apparatus according to claim 17, wherein the decoder logic circuit further includes encoding circuitry to encode the state of the registers except for the first register as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 20

Dependent Claim 23 words

The decoder apparatus according to claim 18, wherein the encoder circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 21

Dependent Claim 29 words

The decoder apparatus according to claim 19, further comprising: a data recovery circuit, coupled to the encoding circuitry, for receiving and holding the binary number and the error condition.

Claim 22

Dependent Claim 106 words

A computer system comprising: a memory; a processor, coupled to the memory, having a network interface which includes a decoder circuit for decoding a phase-encoded digital data signal including a first delay line receiving the phase-encoded digital data signal; a second delay line, operating at a different rate than the first delay line and receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.

Claim 23

Dependent Claim 106 words

A computer system comprising: a memory; a processor, coupled to the memory, having a network interface which includes a decoder circuit for decoding a phase-encoded digital data signal including a first delay line receiving the phase-encoded digital data signal; a second delay line, operating at a different rate than the first delay line and receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.

Claim 24

Dependent Claim 31 words

The decoder apparatus according to claim 21, further comprising: a data recovery circuit, coupled to the decoder logic circuit, for receiving and holding the value extracted by the decoder logic circuit.

Claim 25

Dependent Claim 33 words

The decoder apparatus according to claim 21, wherein the decoder logic circuit includes circuitry configured to sample data at an edge of the received phase-encoded digital data signal in the first delay line.

Claim 26

Dependent Claim 22 words

The decoder apparatus according to claim 21, wherein the decoder logic circuit includes a plurality of registers for holding the sampled data.

Claim 27

Dependent Claim 38 words

The decoder apparatus according to claim 24, wherein the decoder logic circuit further includes encoding circuitry to encode the state of the registers as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 28

Dependent Claim 23 words

The decoder apparatus according to claim 25, wherein the encoding circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 29

Dependent Claim 37 words

The decoder apparatus according to claim 21, wherein the first delay line includes a first number of delay gates coupled in series; and the second delay line includes a first number of delay gates coupled in series.

Claim 30

Dependent Claim 45 words

The decoder apparatus according to claim 27, wherein the delay gates of the first delay line each impart a first delay and the delay gates of the second delay line each impart a second delay, and where the first delay is twice the second delay.

Claim 31

Dependent Claim 32 words

The decoder apparatus according to claim 24, wherein the plurality of registers have a clock input coupled to the first delay line and a data input coupled to the second delay line.

Claim 32

Dependent Claim 37 words

The decoder apparatus according to claim 29, wherein the first delay line includes a first number of delay gates coupled in series; and the second delay line includes a first number of delay gates coupled in series.

Claim 33

Dependent Claim 81 words

The decoder apparatus according to claim 30, wherein each of the registers corresponds to a different one of the delay gates in the first and second delay lines at the same relative position in the series of delay gates; and wherein the clock input of each of the registers connects to the input of the corresponding delay gate in the first delay line and the data input connects to the input of the corresponding delay gate in the second delay line.

Claim 34

Dependent Claim 40 words

The decoder apparatus according to claim 31, wherein a first register of the plurality of registers of the decoder logic circuit includes circuitry configured to latch to the first register an error condition of the received phase-encoded digital data signal.

Claim 35

Dependent Claim 43 words

The decoder apparatus according to claim 32, wherein the decoder logic circuit further includes encoding circuitry to encode a state of the registers except for the first register as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 36

Dependent Claim 23 words

The decoder apparatus according to claim 33, wherein the encoder circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 37

Dependent Claim 29 words

The decoder apparatus according to claim 33, further comprising: a data recovery circuit, coupled to the encoding circuitry, for receiving and holding the binary number and the error condition.

Claim 38

Dependent Claim 76 words

A decoder apparatus for decoding a phase-encoded digital data signal comprising: a timing circuit receiving the phase-encoded digital data signal; a signal viewer circuit receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the timing circuit and signal viewer circuit, configured to sample the phase-encoded digital data signal in the signal viewer circuit at times determined by the timing circuit to extract a value encoded in the received phase-encoded digital data signal.

Claim 39

Dependent Claim 76 words

A decoder apparatus for decoding a phase-encoded digital data signal comprising: a timing circuit receiving the phase-encoded digital data signal; a signal viewer circuit receiving the phase-encoded digital data signal; and a decoder logic circuit, coupled to the timing circuit and signal viewer circuit, configured to sample the phase-encoded digital data signal in the signal viewer circuit at times determined by the timing circuit to extract a value encoded in the received phase-encoded digital data signal.

Claim 40

Dependent Claim 31 words

The decoder apparatus according to claim 36, further comprising: a data recovery circuit, coupled to the decoder logic circuit, for receiving and holding the value extracted by the decoder logic circuit.

Claim 41

Dependent Claim 32 words

The decoder apparatus according to claim 36, wherein the decoder logic circuit includes circuitry configured to sample data at an edge of the received phase-encoded digital data signal in the timing circuit.

Claim 42

Dependent Claim 22 words

The decoder apparatus according to claim 38, wherein the decoder logic circuit includes a plurality of registers for holding the sampled data.

Claim 43

Dependent Claim 38 words

The decoder apparatus according to claim 39, wherein the decoder logic circuit further includes encoding circuitry to encode the state of the registers as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 44

Dependent Claim 23 words

The decoder apparatus according to claim 40, wherein the encoding circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 45

Dependent Claim 31 words

The decoder apparatus according to claim 39, wherein the plurality of registers have a clock input coupled to the timing circuit and a data input coupled to the signal viewer circuit.

Claim 46

Dependent Claim 40 words

The decoder apparatus according to claim 42, wherein a first register of the plurality of registers of the decoder logic circuit includes circuitry configured to latch to the first register an error condition of the received phase-encoded digital data signal.

Claim 47

Dependent Claim 43 words

The decoder apparatus according to claim 43, wherein the decoder logic circuit further includes encoding circuitry to encode the state of the registers except for the first register as a binary number representing the value encoded in the received phase-encoded digital data signal.

Claim 48

Dependent Claim 23 words

The decoder apparatus according to claim 44, wherein the encoder circuitry includes a plurality of NAND gates and a plurality of OR gates.

Claim 49

Dependent Claim 29 words

The decoder apparatus according to claim 44, further comprising: a data recovery circuit, coupled to the encoding circuitry, for receiving and holding the binary number and the error condition.

Claim 50

Independent Claim 56 words

A method of decoding a phase-encoded digital data signal comprising the steps of: receiving the phase-encoded digital data signal; sampling portions of the phase-encoded digital data signal at times determined by a predetermined portion of the phase-encoded digital data signal; and extracting the value encoded in the phase-encoded digital data signal based on the sampled portions.

Claim 51

Independent Claim 56 words

A method of decoding a phase-encoded digital data signal comprising the steps of: receiving the phase-encoded digital data signal; sampling portions of the phase-encoded digital data signal at times determined by a predetermined portion of the phase-encoded digital data signal; and extracting the value encoded in the phase-encoded digital data signal based on the sampled portions.

Claim 52

Dependent Claim 35 words

The method according to claim 47, wherein the sampling step includes the substep of indicating times for sampling portions of the phase-encoded digital data signal based on an edge of the phase-encoded digital data signal.

Claim 53

Dependent Claim 44 words

The method according to claim 47, wherein the sampling step includes the substep of delaying the phase-encoded digital data signal with a first number of serially-coupled gates in a first delay line and a first number of serially-coupled gates in a second delay line.

Claim 54

Dependent Claim 69 words

The method according to claim 49, wherein the first delaying step includes the substeps of imparting a first delay from each of the delay gates in the first delay line to the phase-encoded digital data signal; and imparting a second delay from each of the delay gates in the second delay line to the phase-encoded digital data signal, wherein the first delay is equal to twice the second delay.

Claim 55

Dependent Claim 58 words

The method according to claim 50, wherein the sampling step includes the substep of capturing the portion of the phase-encoded digital data signal at the input of a delay gate in the second delay line when the predetermined portion of the phase-encoded digital data signal reaches the input of the corresponding delay gate in the first delay line.

Claim 56

Dependent Claim 38 words

The method according to claim 50, wherein the setting step includes the substep of adjusting the total delay of the delay gates in the first delay line to equal twice the period of the phase-encoded digital data signal.

Claim 57

Dependent Claim 32 words

The method according to claim 47, wherein the extracting step includes the substep of encoding the extracted value as a binary number representing the value encoded in the phase-encoded digital data signal.

Claim 58

Dependent Claim 31 words

The method according to claim 47, further comprising the step of determining an error condition of the phase-encoded digital data signal based on the value of one of the sampled portions.

Claim 59

Dependent Claim 84 words

The method according to claim 51, wherein the capturing step includes the substeps of detecting a rising edge, formed by a beginning of the phase-encoded digital data signal and an end of a previously received phase-encoded digital data signal, at an input of a delay gate in the first delay line, and latching data at the input of a corresponding delay gate in the second delay line after detecting the rising edge at the input of the delay gate in the first delay line.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-11-14	2004-05-15	2004-11-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-11-14	2008-05-15	2008-11-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-11-14	2012-05-15	2012-11-14	$7700.00	Window Closed / Lapsed

Circuit for detecting and decoding phase encoded digital serial data

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