US6147388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polycide gate structure with intermediate barrier
Assignee: Nokia of America Corp
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Filing: 1997-11-24
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Granted: 2000-11-14
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Expires: 2017-11-24
Abstract
Abstract A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.
Inventors
- 👤 Yi Ma
- 👤 Sailesh Mansinh Merchant
- 👤 Minseok Oh
- 👤 Pradip Kumar Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:35
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664; H10P; H10P95/00; H10P95/90; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
52 words
A CMOS gate structure comprising a multilayered polysilicon structure; a relatively thin nitridized silicide barrier layer formed to cover the multilayered polysilicon structure; and a silicide layer deposited to cover the relatively thin nitridized silicide barrier layer and annealed to exhibit a grain size and structure similar to the multilayered polysilicon structure.
Claim 2
Dependent Claim
52 words
A CMOS gate structure comprising a multilayered polysilicon structure; a relatively thin nitridized silicide barrier layer formed to cover the multilayered polysilicon structure; and a silicide layer deposited to cover the relatively thin nitridized silicide barrier layer and annealed to exhibit a grain size and structure similar to the multilayered polysilicon structure.
Claim 3
Dependent Claim
27 words
A CMOS gate structure as defined in claim 1 wherein the multilayered polysilicon structure includes at least three polysilicon layers formed by varying the polysilicon deposition rate.
Claim 4
Dependent Claim
27 words
A CMOS gate structure as defined in claim 1 wherein the relatively thin nitridized silicide barrier layer comprises a thickness less than or equal to 50 Å.
Claim 5
Dependent Claim
23 words
A CMOS gate structure as defined in claim 1 wherein the relatively thin nitridized silicide barrier layer and silicide layer comprise tungsten silicide.
References Cited (Backward Citations)
US4742020A
Cited
US5153701A
Cited
US5132244A
Cited
US5350698A
Cited
US5633200A
Cited
US5688713A
Cited
US5874353A
Cited
US5846871A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |