Semiconductor integrated circuit with phase adjusting function and system using the same

Claim 2

A phase control circuit comprising a semiconductor integrated circuit and a control unit, wherein said semiconductor integrated circuit comprises: a register for storing a designated value; a delay element group for delaying an input signal by a delay quantity set based on said designated value to output said input signal delayed by said delay quantity as a delay signal; a PLL circuit for inputting said delay signal and a clock signal and for outputting a phase adjustment signal; and a first latch circuit for latching a write data, which is written in another circuit, in response to a latch signal, said other circuit being supplied with said clock signal, a second latch circuit for latching a read data, which is read from said other circuit, in response to said latch signal, wherein said phase adjustment signal is supplied to said delay element group as said input signal and is supplied to said latch circuits as said latch signal, wherein said control unit sequentially supplies predetermined values to said register as said designated value and judges whether said write data is coincident with said read data, each time said predetermined value is supplied to said register, said designated value being held in said register, when both of said read and write data are judged to be coincident with each other.

Claim 3

A phase control circuit according to claim 1, wherein said control unit sequentially supplies said predetermined values to detect a range of said predetermined values in which said write data and said read data are coincident with each other.

Claim 4

A phase control circuit according to claim 2, wherein said control unit selects said designated value from among said predetermined values in the range.

Claim 5

A phase control circuit according to claim 3, wherein said control unit selects an intermediate value among said predetermined values in the range as said designated value.

Claim 6

A phase control circuit including a plurality of semiconductor integrated circuits connected with each other in parallel, and a control section, wherein each of said plurality of semiconductor integrated circuits comprises: a register for storing a designated value; a delay element group for delaying an input signal by a delay quantity set base on said designated value to output said input signal delayed by said delay quantity as a delay signal; a PLL circuit for inputting said delay signal and a clock signal and for outputting a phase adjustment signal; and a first latch circuit for latching a write data, which is written by said control section in another circuit, in response to a latch signal, said other circuit being supplied with said clock signal, a second latch circuit for latching a read data, which is read by said control section from the other circuit, in response to said latch signal, wherein said clock signal is supplied in common to said PLL circuits of said semiconductor integrated circuits, wherein said phase adjustment signal outputted from each of said plurality of PLL circuits is supplied to said first and second latch circuits corresponding to said each PLL circuit as said latch signal wherein said control section sequentially supplies predetermined values to said register of each of said semiconductor integrated circuits as said designated value and judges respectively whether said write data is coincident with said read data, each time said predetermined value is supplied to said register, said designated value being held respectively in said register, when both of said read and write data are judged to be coincident with each other.

Claim 7

A phase control circuit including a plurality of semiconductor integrated circuits connected with each other in parallel, and a control section, wherein each of said plurality of semiconductor integrated circuits comprises: a register for storing a designated value; a delay element group for delaying an input signal by a delay quantity set base on said designated value to output said input signal delayed by said delay quantity as a delay signal; a PLL circuit for inputting said delay signal and a clock signal and for outputting a phase adjustment signal; and a first latch circuit for latching a write data, which is written by said control section in another circuit, in response to a latch signal, said other circuit being supplied with said clock signal, a second latch circuit for latching a read data, which is read by said control section from the other circuit, in response to said latch signal, wherein said clock signal is supplied in common to said PLL circuits of said semiconductor integrated circuits, wherein said phase adjustment signal outputted from each of said plurality of PLL circuits is supplied to said first and second latch circuits corresponding to said each PLL circuit as said latch signal wherein said control section sequentially supplies predetermined values to said register of each of said semiconductor integrated circuits as said designated value and judges respectively whether said write data is coincident with said read data, each time said predetermined value is supplied to said register, said designated value being held respectively in said register, when both of said read and write data are judged to be coincident with each other.

Claim 8

A phase control circuit according to claim 5, wherein said control section sequentially supplies respectively said predetermined values to detect a range of said predetermined values in which said write data and said read data are coincident with each other.

Claim 9

A phase control circuit according to claim 6, wherein said control section selects respectively said designated value from among said predetermined values in the range.

Claim 10

A phase control circuit according to claim 7, wherein said control section selects respectively an intermediate value among said predetermined values in the range as said designated value.

Claim 11

A phase controlling method, comprising the steps of; storing a designated value in a register, delaying an input signal by a delay quantity set based on said designated value to output a signal delayed by said delay quantity as a delay signal, locking phase of a clock signal based on said delay signal to output a phase adjustment signal as said input signal, latching in latch circuits a read data and write data for another circuit in response to said phase adjustment signal as a latch signal, said other circuit being supplied with said clock signal, supplying sequentially predetermined values to said register as said designated value, judging whether the read data and the write data are coincident with each other, holding said predetermined value in said register when the read data and the write data are judged to be coincident with each other.

Claim 12

A phase controlling method, comprising the steps of; storing a designated value in a register, delaying an input signal by a delay quantity set based on said designated value to output a signal delayed by said delay quantity as a delay signal, locking phase of a clock signal based on said delay signal to output a phase adjustment signal as said input signal, latching in latch circuits a read data and write data for another circuit in response to said phase adjustment signal as a latch signal, said other circuit being supplied with said clock signal, supplying sequentially predetermined values to said register as said designated value, judging whether the read data and the write data are coincident with each other, holding said predetermined value in said register when the read data and the write data are judged to be coincident with each other.

Claim 13

A phase control method according to claim 9, wherein said judging step includes: supplying sequentially said predetermined values to detect a range of said predetermined values in which said write data and said read data are coincident with each other.

Claim 14

A phase control method according to claim 10, wherein said judging step includes: selecting said designated value from among said predetermined values in the range.

Claim 15

A phase control method according to claim 11, wherein said judging step includes: selecting an intermediate value among said predetermined values in the range as said designated value.

Claim 16

A phase controlling method, comprising the steps of; supplying a clock signal in common to a plurality of PLL circuits, storing a designated value in a register corresponding to each of said PLL circuits, delaying an input signal by a delay quantity set based on said designated value to output a signal delayed by said delay quantity as a delay signal, supplying said delay signal to each of said PLL circuits to output a phase adjustment signal, latching in latch circuits corresponding to said each PLL circuit a read data and write data for another circuit in response to said phase adjustment signal as a latch signal, said other circuit being supplied with said clock signal, supplying sequentially predetermined values to said register as said designated value, judging respectively whether the read data and the write data are coincident with each other, holding said predetermined value in said register when the read data and the write data are judged to be coincident with each other.

Claim 17

A phase controlling method, comprising the steps of; supplying a clock signal in common to a plurality of PLL circuits, storing a designated value in a register corresponding to each of said PLL circuits, delaying an input signal by a delay quantity set based on said designated value to output a signal delayed by said delay quantity as a delay signal, supplying said delay signal to each of said PLL circuits to output a phase adjustment signal, latching in latch circuits corresponding to said each PLL circuit a read data and write data for another circuit in response to said phase adjustment signal as a latch signal, said other circuit being supplied with said clock signal, supplying sequentially predetermined values to said register as said designated value, judging respectively whether the read data and the write data are coincident with each other, holding said predetermined value in said register when the read data and the write data are judged to be coincident with each other.

Claim 18

A phase control method according to claim 13, wherein said judging step includes: supplying sequentially said predetermined values to detect a range of said predetermined values in which said write data and said read data are coincident with each other.

Claim 19

A phase control method according to claim 14, wherein said judging step includes: selecting said designated value from among said predetermined values in the range.