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Low resistivity semiconductor barrier layers and manufacturing method therefor

Assignee: Advanced Micro Devices Inc
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Filing: 1998-10-05
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Granted: 2000-11-07
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Expires: 2018-10-05
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Abstract

Abstract A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.

Inventors

  • 👤 Sergey D. Lopatin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:41
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/40; H10W20/41; H10W20/42; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W20/4432; H10W20/4435

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 95 words
A semiconductor comprising: a semiconductor substrate; a dielectric layer formed on a region of said semiconductor substrate; an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a conductive area in the semiconductor; a barrier layer on said dielectric layer in said opening, including along said walls, and in conductive contact with said conductive area, said barrier layer containing a first metal from Group VIII B combined with a second metal; and a conductive material in contact with said barrier layer, said conductive material substantially fills said opening.
Claim 2
Dependent Claim 95 words
A semiconductor comprising: a semiconductor substrate; a dielectric layer formed on a region of said semiconductor substrate; an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a conductive area in the semiconductor; a barrier layer on said dielectric layer in said opening, including along said walls, and in conductive contact with said conductive area, said barrier layer containing a first metal from Group VIII B combined with a second metal; and a conductive material in contact with said barrier layer, said conductive material substantially fills said opening.
Claim 3
Dependent Claim 22 words
The semiconductor as claimed in claim 1 wherein said second metal includes a Group V B element combined in said barrier layer.
Claim 4
Dependent Claim 22 words
The semiconductor as claimed in claim 1 wherein said second metal includes a Group VI B element combined in said barrier layer.
Claim 5
Dependent Claim 27 words
The semiconductor as claimed in claim 1 wherein said second metal includes between 0.2% to 4% of a Group V B element combined in said barrier layer.
Claim 6
Dependent Claim 27 words
The semiconductor as claimed in claim 1 wherein said second metal includes between 0.2% to 4% of a Group VI B element combined in said barrier layer.
Claim 7
Dependent Claim 20 words
The semiconductor as claimed in claim 1 wherein said conductive material is a material containing a Group I B element.
Claim 8
Dependent Claim 34 words
The semiconductor as claimed in claim 1 wherein said conductive material is a material selected from the group comprising aluminum, tungsten, doped polysilicon, copper-base alloys, gold, gold-base alloys, silver, silver-base alloys, and combinations thereof.
Claim 9
Dependent Claim 99 words
A semiconductor comprising: a semiconductor substrate; a dielectric layer formed on a region of said semiconductor substrate; an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said region on said semiconductor substrate; a barrier layer on said dielectric layer in said opening, including along said walls, said barrier layer containing therefore a first metal selected from a group consisting of cobalt, nickel, palladium and combinations thereof combined with a second metal; and a conductive material in contact with said barrier layer, said conductive material substantially fills said opening.
Claim 10
Dependent Claim 99 words
A semiconductor comprising: a semiconductor substrate; a dielectric layer formed on a region of said semiconductor substrate; an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said region on said semiconductor substrate; a barrier layer on said dielectric layer in said opening, including along said walls, said barrier layer containing therefore a first metal selected from a group consisting of cobalt, nickel, palladium and combinations thereof combined with a second metal; and a conductive material in contact with said barrier layer, said conductive material substantially fills said opening.
Claim 11
Dependent Claim 19 words
The semiconductor as claimed in claim 8 wherein said second metal includes a tantalum alloyed to said barrier layer.
Claim 12
Dependent Claim 27 words
The semiconductor as claimed in claim 8 wherein said second metal includes a metal alloyed with said barrier layer selected from the group comprising molybdenum and tungsten.
Claim 13
Dependent Claim 23 words
The semiconductor as claimed in claim 8 wherein said second metal includes between 0.2% to 4% of tantalum alloyed in said barrier layer.
Claim 14
Dependent Claim 32 words
The semiconductor as claimed in claim 8 wherein said second metal includes between 0.2% to 4% of a metal alloyed with said barrier layer selected from the group comprising molybdenum and tungsten.
Claim 15
Dependent Claim 25 words
The semiconductor as claimed in claim 8 wherein said conductive material is a material selected from the group comprising copper, silver, gold, and combinations thereof.
Claim 16
Dependent Claim 34 words
The semiconductor as claimed in claim 8 wherein said conductive material is a material selected from the group comprising aluminum, tungsten, doped polysilicon, copper-base alloys, gold, gold-base alloys, silver, silver-base alloys, and combinations thereof.

References Cited (Backward Citations)

US5134460A Cited
US5094981A Cited
US5858868A Cited
US5623166A Cited
US5695810A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-11-07 2004-05-08 2004-11-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-11-07 2008-05-08 2008-11-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-11-07 2012-05-08 2012-11-07 $7700.00 Window Closed / Lapsed

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