Patent JPS58199860A successfully refreshed from Google Patents.
Patent US6141762A successfully refreshed from Google Patents.
US6141762A
Expired / Lapsed
US
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Power reduction in a multiprocessor digital signal processor based on processor load
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-08-03
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Granted: 2000-10-31
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Expires: 2018-08-03
Abstract
Abstract Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.
Inventors
- 👤 Christopher J. Nicol
- 👤 Kanwar Jit Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:03
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/329; G06F1/3296; G06F9/00; G06F9/06; G06F9/46; G06F9/50; G06F9/5005; G06F9/5027; G06F9/505; G06F9/5094; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 51
Claim 1
Independent Claim
87 words
A method executed within a system for controlling power consumption of a sub-circuit of said system comprising the steps of: ascertaining time allotted for carrying out an assigned task; determining a lowest frequency at which or above which the sub-circuit must operate in order to complete execution of the assigned task within the allotted time; and based on characteristics of the sub-circuit, setting a supply voltage that is applied to the sub-circuit to a lowest level that insures proper operation of the sub-circuit at the determined frequency.
Claim 2
Independent Claim
87 words
A method executed within a system for controlling power consumption of a sub-circuit of said system comprising the steps of: ascertaining time allotted for carrying out an assigned task; determining a lowest frequency at which or above which the sub-circuit must operate in order to complete execution of the assigned task within the allotted time; and based on characteristics of the sub-circuit, setting a supply voltage that is applied to the sub-circuit to a lowest level that insures proper operation of the sub-circuit at the determined frequency.
Claim 3
Dependent Claim
35 words
The method of claim 1 further comprising the step of executing said task after said voltage is set, and a frequency at which or above which the sub-circuit operates is set to said determined frequency.
Claim 4
Dependent Claim
107 words
The method of claim 1, carried out in a multiprocessor sub-circuit, wherein said assigned task comprises a plurality of sub-tasks, the method further comprising the step of apportioning said sub-tasks among processors of said multiprocessor sub-circuit, resulting in one of said processors carrying the largest load of sub-tasks processing, compared to the sub-tasks processing load of others of said processors, where said step of apportioning is executed prior to said step of determining, and said step of determining ascertains the lowest frequency that, when employed at the processor carrying the largest load of sub-tasks processing, is sufficient to complete its assigned sub-tasks processing within the allotted time.
Claim 5
Dependent Claim
21 words
The method of claim 3 further comprising the step of assigning the subtasks to said processors in accordance with said apportioning.
Claim 6
Dependent Claim
15 words
The method of claim 1, wherein said steps are executed in a multiprocessor integrated circuit.
Claim 7
Dependent Claim
20 words
The method of claim 5 where said steps are executed in said processor under control of a real-time operating system.
Claim 8
Dependent Claim
41 words
The method of claim 6 wherein assigned task comprises a plurality of sub-tasks and said method further comprising a step, executed in said processor under control of said real-time operating system, of apportioning said sub-tasks among processors of said multiprocessor sub-circuit.
Claim 9
Dependent Claim
19 words
The method of claim 1 wherein said steps are executed in a circuit that comprises distinct, cooperating, processing units.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein the determined frequency assumes values that are multiples of a preset frequency increment.
Claim 11
Dependent Claim
33 words
The method of claim 1 wherein the step of setting a supply voltage is sensitive to an operational state of two circuits that are identical except that one is slower than the other.
Claim 12
Dependent Claim
20 words
The method of claim 10, carried out in an integrated circuit, wherein said two circuits are within said integrated circuit.
Claim 13
Dependent Claim
46 words
The method of claim 10 wherein the step of setting a supply voltage adjusts the supply voltage to cause the slower of the two circuits to be at a failed operational state, and the other of the two circuits to be at a working operational state.
Claim 14
Dependent Claim
152 words
The method of claim 2 further comprising the steps of: determining a new lowest frequency, when a new task is assigned, at which or above which the sub-circuit must operate in order to complete execution of the assigned task within the allotted time; comparing the lowest frequency to the new lowest frequency to determine whether a new operating frequency should be set for said sub-circuit; when said step of comparing determines that the new lowest frequency is lower than said lowest frequency, reducing the frequency at which said sub-circuit is set to operate and, thereafter, reducing the supply voltage that is applied to the sub-circuit; and when said step of comparing determines that the new lowest frequency must be higher than said lowest frequency, increasing the supply voltage that is applied to the sub-circuit and, thereafter, increasing the frequency at which said sub-circuit is set to operate to said new lowest frequency.
Claim 15
Dependent Claim
21 words
The method of claim 1 wherein the characteristics of the sub-circuit are expressed as a relationship between frequency and supply voltage.
Claim 16
Dependent Claim
19 words
The method of claim 1 further comprising the step of converting output levels of said sub-circuit to standardized levels.
Claim 17
Dependent Claim
23 words
The method of claim 1 further comprising the step of synchronizing output signals of said sub-circuit to a timing signal of said system.
Claim 18
Dependent Claim
155 words
A circuit that includes a processor, comprising: a controller, responsive to an applied task and to a specification of a time interval, where duration of at most said time interval is necessary for execution of said applied task, for developing a frequency of operation for said processor that is the lowest frequency of operation that allows completion of said applied task within said time interval; a calibration circuit responsive to said controller for directing creation of a supply voltage for said processor, and a power supply responsive to said calibration circuit, for developing said supply voltage for said processor and applying said supply voltage to said processor; wherein said controller directs said processor to execute said task after said supply voltage is applied to said processor and the frequency of a clock applied to said processor is set to said lowest frequency of operation that allows completion of said applied task within said time interval.
Claim 19
Dependent Claim
155 words
A circuit that includes a processor, comprising: a controller, responsive to an applied task and to a specification of a time interval, where duration of at most said time interval is necessary for execution of said applied task, for developing a frequency of operation for said processor that is the lowest frequency of operation that allows completion of said applied task within said time interval; a calibration circuit responsive to said controller for directing creation of a supply voltage for said processor, and a power supply responsive to said calibration circuit, for developing said supply voltage for said processor and applying said supply voltage to said processor; wherein said controller directs said processor to execute said task after said supply voltage is applied to said processor and the frequency of a clock applied to said processor is set to said lowest frequency of operation that allows completion of said applied task within said time interval.
Claim 20
Dependent Claim
25 words
The apparatus of claim 17 wherein said processor, said calibration circuit and all amplifying elements of said power supply are on a single circuit board.
Claim 21
Dependent Claim
25 words
The apparatus of claim 17 wherein said processor, said calibration circuit and all amplifying elements of said power supply are manufactured within an integrated circuit.
Claim 22
Dependent Claim
33 words
The apparatus of claim 17 further comprising a level converter circuit interposed between input/output ports of said circuit and said processor, to convert voltages levels passing between said input/output ports and said processor.
Claim 23
Dependent Claim
58 words
The apparatus of claim 17 wherein said controller includes a generator of clock signals that develops a first clock signal having a first frequency and applied to said calibration circuits, and a second clock signal having a second frequency applied to said processor, wherein the second frequency is set to said first frequency or to a lower frequency.
Claim 24
Dependent Claim
80 words
The apparatus of claim 21 wherein said controller directs said calibration circuit to decrease said supply voltage when an applied task results in said controller developing a frequency of operation for said processor that is lower than an existing frequency of operation for said processor, and when said calibration circuit is directed to decrease said supply voltage, said controller sets the second frequency to a frequency that is lower than said first frequency prior to said supply voltage being decreased.
Claim 25
Dependent Claim
74 words
The apparatus of claim 21 wherein said controller directs said calibration circuit to increase said supply voltage when an applied task results in said controller developing a frequency of operation for said processor that is higher than an existing frequency of operation for said processor, and when said calibration circuit is directed to increase said supply voltage, said controller sets the second frequency to said first frequency only after said supply voltage is increased.
Claim 26
Dependent Claim
80 words
The apparatus of claim 17 wherein said controller directs said calibration circuit to decrease said supply voltage when an applied task results in said controller developing a frequency of operation for said processor that is lower than an existing frequency of operation for said processor, and when said calibration circuit is directed to decrease said supply voltage, said controller sets the second frequency to a frequency that is lower than said first frequency prior to said supply voltage being decreased.
Claim 27
Dependent Claim
74 words
The apparatus of claim 17 wherein said controller directs said calibration circuit to increase said supply voltage when an applied task results in said controller developing a frequency of operation for said processor that is higher than an existing frequency of operation for said processor, and when said calibration circuit is directed to increase said supply voltage, said controller sets the second frequency to said first frequency only after said supply voltage is increased.
Claim 28
Dependent Claim
43 words
The apparatus of claim 17 wherein said task includes a plurality of sub-tasks, said processor comprises a plurality of processing elements, said controller partitions said sub-tasks among said processing elements and develops said frequency of operation for said processor based on said partitioning.
Claim 29
Dependent Claim
60 words
The apparatus of claim 26 wherein said controller develops said frequency of operation for said processor by evaluating the lowest frequency of operation for a most-burdened processing element that would still complete execution within said time interval, wherein the most-burdened processing element is a processing element to which sub-tasks are allocated that require, in the aggregate, the most processing time.
Claim 30
Dependent Claim
29 words
The apparatus of claim 27 wherein said controller partitions said sub-tasks with the goal of partitioning the sub-tasks evenly, based on a processing burden criterion, among the processing elements.
Claim 31
Dependent Claim
18 words
The apparatus of claim 26 further comprising a level converter coupled to input/output ports of said processing elements.
Claim 32
Dependent Claim
28 words
The apparatus of claim 26 wherein said processing elements, said controller, said calibration circuit and all amplifying elements of said power supply are manufactured within an integrated circuit.
Claim 33
Dependent Claim
46 words
The apparatus of claim 17 wherein said calibration circuit includes two copies of at least a portion of said processor, wherein one copy is manufactured to operate at fast as said portion operates within said processor, and the other copy is manufactured to operate more slowly.
Claim 34
Dependent Claim
80 words
The apparatus of claim 17 wherein said processor comprises N processing elements, said controller comprises N controller sub-modules, said calibration circuit comprises N calibration circuit sub-modules, and said power supply comprises N power supply modules, and wherein the i-th calibration circuit sub-module is responsive to the i-th controller sub-module and directs the i-th power supply module, the i-th power supply module provides power to the i-th processing element, and the i-th processing element is responsive to the i-th controller sub-module.
Claim 35
Dependent Claim
25 words
The apparatus of claim 32 wherein said processor, said calibration circuit and all amplifying elements of said power supply are manufactured within an integrated circuit.
Claim 36
Dependent Claim
32 words
The apparatus of claim 33 further comprising a processing element for accepting said task and, when said task comprises a plurality of sub-tasks, for partitioning said sub-tasks among the N processing elements.
Claim 37
Dependent Claim
31 words
The apparatus of claim 34 wherein said processing element for accepting said task, processor, said calibration circuit and all amplifying elements of said power supply are manufactured within an integrated circuit.
Claim 38
Dependent Claim
25 words
The apparatus of claim 32 further comprising means within said controller for turning supply power off to at least one of said N processing elements.
Claim 39
Dependent Claim
27 words
The apparatus of claim 32 further comprising a level converter associated with each of said processing elements and coupled to input/output ports of said associated processing elements.
Claim 40
Dependent Claim
15 words
The apparatus of claim 37 further comprising a synchronization circuit coupled to said level converters.
Claim 41
Dependent Claim
71 words
A circuit comprising: a controller processing element; a plurality of task-handling processing elements; a calibration circuit responsive to said controller processing element for directing creation of a supply voltage for said processing elements; and a power supply circuit, responsive to said calibration circuit, for developing a supply voltage for said task-handling processing elements; wherein said controller processing element directs said task-handling processing elements to execute tasks at a selected processing frequency.
Claim 42
Dependent Claim
71 words
A circuit comprising: a controller processing element; a plurality of task-handling processing elements; a calibration circuit responsive to said controller processing element for directing creation of a supply voltage for said processing elements; and a power supply circuit, responsive to said calibration circuit, for developing a supply voltage for said task-handling processing elements; wherein said controller processing element directs said task-handling processing elements to execute tasks at a selected processing frequency.
Claim 43
Dependent Claim
22 words
The circuit of claim 39 wherein said controller processing element, task-handling processing elements, and calibration circuit are on a single circuit board.
Claim 44
Dependent Claim
21 words
The circuit of claim 39 wherein said controller processing element, task-handling processing elements, and calibration circuit are within an integrated circuit.
Claim 45
Dependent Claim
21 words
The circuit of claim 39 further comprising a level converter interposed between said controller processing element and said task-handling processing elements.
Claim 46
Dependent Claim
153 words
A circuit that includes a processor, comprising: first means, responsive to an applied task and to a specification for a time interval, where duration of at most said time interval is necessary to execute said task, for developing a frequency of operation for said processor that is the lowest frequency of operation that allows completion of said applied task within said time interval; second means responsive to said first means for directing creation of a supply voltage for said processor, and third means, responsive to said second means, for developing said supply voltage for said processor and applying said supply voltage to said processor; wherein said first means directs said processor to execute said task after said supply voltage is applied to said processor and the frequency of a clock applied to said processor is set to said lowest frequency of operation that allows completion of said applied task within said time interval.
Claim 47
Dependent Claim
153 words
A circuit that includes a processor, comprising: first means, responsive to an applied task and to a specification for a time interval, where duration of at most said time interval is necessary to execute said task, for developing a frequency of operation for said processor that is the lowest frequency of operation that allows completion of said applied task within said time interval; second means responsive to said first means for directing creation of a supply voltage for said processor, and third means, responsive to said second means, for developing said supply voltage for said processor and applying said supply voltage to said processor; wherein said first means directs said processor to execute said task after said supply voltage is applied to said processor and the frequency of a clock applied to said processor is set to said lowest frequency of operation that allows completion of said applied task within said time interval.
Claim 48
Independent Claim
37 words
A method for operating a processor comprising the step of applying a supply voltage to said processor as a function of frequency necessary to operate said processor to complete an assigned task within an assigned time interval.
Claim 49
Independent Claim
37 words
A method for operating a processor comprising the step of applying a supply voltage to said processor as a function of frequency necessary to operate said processor to complete an assigned task within an assigned time interval.
Claim 50
Dependent Claim
15 words
The method of claim 44 wherein said function substantially minimizes power consumption in said processor.
Claim 51
Dependent Claim
25 words
The method of claim 44 wherein said frequency is set to a minimum level that still enables completing said task in an allotted time interval.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |