US6141691A
Expired / Lapsed
US
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Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
Assignee: Avid Technology Inc
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Filing: 1998-04-03
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Granted: 2000-10-31
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Expires: 2018-04-03
Abstract
Abstract An interface enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls the flow of data between the processing elements. The flow control allows the processing elements to be data independent, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format, or other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats and precisions. Flow of data between processing elements may be controlled by handshake signals indicating whether the data output by the sender is valid and whether the receiver can receive data. The sender transmits data and asserts a valid signal along with the data in response to a request signal from the receiver. The request signal may be asserted by the receiver and responded to asynchronously by the sender with the transmission of the data by the sender. As a result, the sender and receiver are decoupled, thus enabling high speed data transmission and time division multiplexing of data across the interconnect. The sender also may transfer command data. A valid command signal is to indicate the present of command data.
Inventors
- 👤 Craig R. Frink
- 👤 Raymond D. Cacciatore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:12
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/60; H04N21/63; H04N21/643
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
128 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver and asynchronous with the reference clock signal indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum.
Claim 2
Dependent Claim
128 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver and asynchronous with the reference clock signal indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum.
Claim 3
Dependent Claim
37 words
The output interface of claim 1, wherein the output comprises: data lines for carrying the datum; a boundary signal line for carrying the boundary signal; and a valid data signal line for carrying the valid data signal.
Claim 4
Dependent Claim
19 words
The output interface of claim 2, wherein the input comprises: a request signal line for carrying the request signal.
Claim 5
Dependent Claim
29 words
The output interface of claim 1, wherein the output further provides a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 6
Dependent Claim
32 words
The output interface of claim 4, wherein the controller, after receipt of the request signal, directs command data to the output and asserts the valid command signal in association with the datum.
Claim 7
Dependent Claim
28 words
The output interface of claim 4, further comprising means for encoding packets of data using a combined state of the valid data signal and the valid command signal.
Claim 8
Dependent Claim
61 words
The output interface of claim 6, further comprising a phase-lock loop having an input for receiving the reference clock signal and an output for providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 9
Dependent Claim
55 words
The output interface of claim 7, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the output interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an input interface receiving the data from the output interface.
Claim 10
Dependent Claim
28 words
The output interface of claim 8, further comprising means for time division multiplexing data onto the output interface at the rate of the output of the phase-lock loop.
Claim 11
Dependent Claim
84 words
The output interface of claim 4, further comprising: a counting circuit having a first input for receiving a value to be loaded to provide an output, wherein the output indicates a number of samples of the output data for which the command data is valid, and control logic for tracking a number of samples processed by a processing element and for generating the control signal to the processing element after the processing element outputs the last sample for which the command data is valid.
Claim 12
Dependent Claim
61 words
The output interface of claim 1, further comprising a phase-lock loop having an input for receiving the reference clock signal and an output for providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 13
Dependent Claim
55 words
The output interface of claim 11, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the output interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an input interface receiving the data from the output interface.
Claim 14
Dependent Claim
28 words
The output interface of claim 12, further comprising means for time division multiplexing data onto the output interface at the rate of the output of the phase-lock loop.
Claim 15
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal asynchronous with the reference clock signal and indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted and at a rate defined by the reference clock signal.
Claim 16
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal asynchronous with the reference clock signal and indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted and at a rate defined by the reference clock signal.
Claim 17
Dependent Claim
38 words
The input interface of claim 14, wherein the input comprises: data lines for carrying the datum; a boundary signal line for carrying the boundary signal; and a valid data signal output line for carrying the valid data signal.
Claim 18
Dependent Claim
19 words
The input interface of claim 15, wherein the output comprises: a request signal line for carrying the request signal.
Claim 19
Dependent Claim
29 words
The input interface of claim 14, wherein the input further receives a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 20
Dependent Claim
37 words
The input interface of claim 17, wherein the controller issues the request signal when the input interface is capable of receiving data and reads the command data from the input when the valid command signal is asserted.
Claim 21
Dependent Claim
27 words
The input interface of claim 17, further comprising means for decoding packets defined by a combined state of the valid data signal and the valid command signal.
Claim 22
Dependent Claim
60 words
The input interface of claim 19, further comprising a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 23
Dependent Claim
55 words
The input interface of claim 20, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the input interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an output interface providing the data to the input interface.
Claim 24
Dependent Claim
26 words
The input interface of claim 21, further comprising means for demultiplexing time division multiplexed data on the input interface using the output of the phase-lock loop.
Claim 25
Dependent Claim
84 words
The input interface of claim 17, further comprising: a counting circuit having a first input for receiving a value to be loaded to provide an output, wherein the output indicates a number of samples of the received data for which the command data is valid, and control logic for tracking a number of samples processed by a processing element and for generating the control signal to the processing element after the processing element outputs the last sample for which the command data is valid.
Claim 26
Dependent Claim
60 words
The input interface of claim 14, further comprising a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 27
Dependent Claim
55 words
The input interface of claim 24, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the input interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an output interface providing the data to the input interface.
Claim 28
Dependent Claim
26 words
The input interface of claim 25, further comprising means for demultiplexing time division multiplexed data on the input interface using the output of the phase-lock loop.
Claim 29
Dependent Claim
114 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with data and indicating whether the associated data is valid and a valid command signal associated with a command data and indicating whether the associated command data is valid command data; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that transfers data with one of the valid data signal and the valid command signal asserted when a request signal is received.
Claim 30
Dependent Claim
114 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with data and indicating whether the associated data is valid and a valid command signal associated with a command data and indicating whether the associated command data is valid command data; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that transfers data with one of the valid data signal and the valid command signal asserted when a request signal is received.
Claim 31
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender data and a boundary signal indicating whether the data defines a boundary of a sample of the data and a valid data signal associated with the data and indicating whether the data is valid and a valid command signal associated with the data and indicating whether the data is valid command data; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when one of the valid data signal and the valid command signal is asserted.
Claim 32
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender data and a boundary signal indicating whether the data defines a boundary of a sample of the data and a valid data signal associated with the data and indicating whether the data is valid and a valid command signal associated with the data and indicating whether the data is valid command data; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when one of the valid data signal and the valid command signal is asserted.
Claim 33
Dependent Claim
119 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum, wherein the output further provides a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 34
Dependent Claim
119 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum, wherein the output further provides a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 35
Dependent Claim
32 words
The output interface of claim 29, wherein the controller, after receipt of the request signal, directs command data to the output and asserts the valid command signal in association with the datum.
Claim 36
Dependent Claim
28 words
The output interface of claim 29, further comprising means for encoding packets of data using a combined state of the valid data signal and the valid command signal.
Claim 37
Dependent Claim
90 words
The output interface of claim 31, wherein the output further comprises a reference clock signal, wherein the data is output by the output interface at a rate defined by the reference clock signal, the output interface further comprising: a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 38
Dependent Claim
55 words
The output interface of claim 32, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the output interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an input interface receiving the data from the output interface.
Claim 39
Dependent Claim
28 words
The output interface of claim 33, further comprising means for time division multiplexing data onto the output interface at the rate of the output of the phase-lock loop.
Claim 40
Dependent Claim
84 words
The output interface of claim 29, further comprising: a counting circuit having a first input for receiving a value to be loaded to provide an output, wherein the output indicates a number of samples of the output data for which the command data is valid, and control logic for tracking a number of samples processed by a processing element and for generating the control signal to the processing element after the processing element outputs the last sample for which the command data is valid.
Claim 41
Dependent Claim
171 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 42
Dependent Claim
171 words
An output interface for a sender of data, comprising: an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 43
Dependent Claim
55 words
The output interface of claim 36, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the output interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an input interface receiving the data from the output interface.
Claim 44
Dependent Claim
28 words
The output interface of claim 37, further comprising means for time division multiplexing data onto the output interface at the rate of the output of the phase-lock loop.
Claim 45
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted wherein the input further receives a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 46
Dependent Claim
124 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted wherein the input further receives a valid command signal associated with a datum and indicating whether the associated datum is valid command data.
Claim 47
Dependent Claim
37 words
The input interface of claim 39, wherein the controller issues the request signal when the input interface is capable of receiving data and reads the command data from the input when the valid command signal in asserted.
Claim 48
Dependent Claim
27 words
The input interface of claim 39, further comprising means for decoding packets defined by a combined state of the valid data signal and the valid command signal.
Claim 49
Dependent Claim
87 words
The input interface of claim 41, wherein the input further comprises a reference clock signal and wherein the controller reads data at a rate defined by the reference clock signal, the input interface further comprising: a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 50
Dependent Claim
55 words
The input interface of claim 42, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the input interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an output interface providing the data to the input interface.
Claim 51
Dependent Claim
26 words
The input interface of claim 43, further comprising means for demultiplexing time division multiplexed data on the input interface using the output of the phase-lock loop.
Claim 52
Dependent Claim
84 words
The input interface of claim 39, further comprising: a counting circuit having a first input for receiving a value to be loaded to provide an output, wherein the output indicates a number of samples of the received data for which the command data is valid, and control logic for tracking a number of samples processed by a processing element and for generating the control signal to the processing element after the processing element outputs the last sample for which the command data is valid.
Claim 53
Dependent Claim
174 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal indicating a request for transfer of data from the sender; a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted, wherein the data is read by the controller at a rate defined by the reference clock signal; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 54
Dependent Claim
174 words
An input interface for a receiver of data, comprising: an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal indicating a request for transfer of data from the sender; a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted, wherein the data is read by the controller at a rate defined by the reference clock signal; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop.
Claim 55
Dependent Claim
55 words
The input interface of claim 46, wherein the rate of the output of the phase-lock loop is a non-integer multiple of the rate of the reference clock signal, and the input interface further comprises means for synchronizing the phase-lock loop with a phase-lock loop in an output interface providing the data to the input interface.
Claim 56
Dependent Claim
26 words
The input interface of claim 47, further comprising means for demultiplexing time division multiplexed data on the input interface using the output of the phase-lock loop.
References Cited (Backward Citations)
US4760573A
Cited
EP0303751A1
Cited
US5222102A
Cited
EP0579389A1
Cited
US5551016A
Cited
US5555266A
Cited
US5826053A
Cited
US5847779A
Cited
EP0692764A1
Cited
US5903324A
Cited
EP0700003A2
Cited
US5651001A
Cited
WO1998059494A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |