Patent EP0107874A1 successfully refreshed from Google Patents.
EP0700003A2
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Data processor with controlled burst memory accesses and method therefor
Assignee: Motorola Solutions Inc
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Filing: 1995-08-25
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Granted: —
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Expires: 2015-08-25
Abstract
Abstract A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).
Inventors
- 👤 Chinh Hoang Le
- 👤 James B. Eifert
- 👤 Wallace B. Harwood, Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441; G06F13/20; G06F13/28; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
277 words
A data processor (21) with controlled burst memory accesses, comprising: an internal data bus (31) having a first predetermined width; a central processing unit (30) having a data path of said first predetermined width coupled to said internal data bus (31), for performing instructions and accessing memory, and having a control output terminal for providing a memory access request signal to request an access of a first predetermined number of data elements in a corresponding first predetermined number of accesses; a chip select circuit (32) coupled to said central processing unit (30), having a control output for providing a port size signal indicative of whether an external memory (24) coupled to an external data bus (22) has said first predetermined width or a second predetermined width; and an external bus interface circuit (33) having a first port coupled to said internal data bus (31), a second port coupled to said external data bus (22), and control input terminals for receiving said memory access request signal and said port size signal; said external bus interface circuit (33) responsive to said memory access request signal to provide said first predetermined number of data elements each having said first predetermined width to said internal data bus (31); said external bus interface circuit (33) further responsive to said port size signal either to perform said first predetermined number of accesses to said external memory (24) if said port size signal indicates that said external memory (24) has said first predetermined width, or to perform a second predetermined number of accesses to said external memory (24) if said port size signal indicates that said external memory (24) has said second predetermined width.
Claim 2
Dependent Claim
28 words
The data processor (21) of claim 1 wherein said external bus interface circuit (33) further performs said second predetermined number of accesses in a plurality of burst cycles.
Claim 3
Dependent Claim
32 words
The data processor (21) of claim 2 wherein said external bus interface circuit (33) performs a number of burst cycles dependent on a starting address provided by said central processing unit (30).
Claim 4
Dependent Claim
258 words
An integrated circuit data processor (21) with controlled burst memory accesses, comprising: an internal bus (31); a first internal bus master device (30) coupled to said internal bus (31), for performing a first burst access having a predetermined number of data beats by providing a first burst request signal to a control output terminal thereof; a second internal bus master device (34) coupled to said internal bus (31), for performing a second burst access having a variable number of data beats by providing a second burst request signal to an output terminal thereof, said second internal bus master device (34) indicating a start and an end of said second burst access; and an external bus interface circuit (33) having a first port coupled to said internal bus (31), a second port coupled to an external data bus (22), control input terminals for receiving said first and second burst request signals, and a control output terminal for providing a fix signal; said external bus interface circuit (33) activating said fix signal and performing at least one corresponding external burst cycle to transfer said predetermined number of data beats between said first internal bus master device (30) and said external data bus (22) in response to said first burst request signal; said external bus interface circuit (33) keeping said fix signal inactive and performing at least one external burst cycle to transfer said variable number of data beats between said second internal bus master device (34) and said external data bus (22) in response to said second burst request signal.
Claim 5
Dependent Claim
37 words
The integrated circuit data processor (21) of claim 4 wherein said first internal bus master device (30) comprises a cache (35) and provides said first burst request signal to perform a line fill of said cache (35).
Claim 6
Dependent Claim
23 words
The integrated circuit data processor (21) of claim 4 wherein said second internal bus master device (34) comprises a direct memory access controller.
Claim 7
Dependent Claim
284 words
An external bus interface circuit (33) comprising: control input terminals for receiving first and second burst request signals; an address input terminal for receiving a burst address from an internal bus (31); an address output terminal for providing an address to an external bus (22, 23); a control output terminal for providing a fix signal; an address transfer element (122) having an input coupled to said internal bus (31), a control input terminal, and an output coupled to said external bus (22, 23); a data transfer element (123) having a first terminal coupled to said internal bus (31), a control input terminal, and a second terminal coupled to said external bus (22, 23); and a state machine (124) coupled to said control input terminals and said control output terminal of said external bus interface circuit (33); said state machine (124) activating said fix signal and performing at least one corresponding external burst cycle by activating said address (122) and data (123) transfer elements to transfer a predetermined number of data beats between said internal bus (31) and said external bus (22, 23) in response to said first burst request signal; said external bus interface circuit (33) keeping said fix signal inactive and performing at least one external burst cycle by activating said address (122) and data (123) transfer elements to transfer a variable number of data beats between said internal bus (31) and said external bus (22, 23) in response to said second burst request signal; whereby said external bus interface circuit (33) may be variously used in integrated circuit data processors with only a fixed burst access device, only a variable burst access device, or with both fixed and variable burst access devices.
Claim 8
Independent Claim
221 words
A method for executing controlled burst memory accesses in a data processor (21), the data processor (21) having a bus master device (30) with a data path of a first predetermined width, the data processor (21) for being coupled to an external memory (24) having a second predetermined width, comprising the steps of: detecting a burst access by said bus master device (30) to the external memory (24); receiving and storing a starting address of said burst access; performing first and second burst accesses each having a first predetermined number of beats in response to said starting address having a first predetermined alignment; performing third, fourth, and fifth burst accesses in response to said starting address having a second predetermined alignment; said third, fourth, and fifth burst accesses having third, fourth, and fifth predetermined numbers of beats, respectively; and responding to said burst access by the bus master device (30) by transferring a plurality of data elements of said first predetermined width between the external memory (24) and said bus master device (30) during each beat of said burst access, said plurality of data elements transferred during either, said first and second burst accesses if said starting address has said first predetermined alignment, or during said third, fourth, and fifth burst accesses if said starting address has said second predetermined alignment.
Claim 9
Independent Claim
157 words
A method for executing controlled burst memory accesses in a data processor (21), comprising the steps of: detecting a memory access request requiring a first predetermined number of data elements by a first internal bus master device (30) of the data processor (21); activating a control signal and performing at least one corresponding external fixed burst cycle to provide said first predetermined number of data elements to said first internal bus master device (30) in response to a first memory access request signal; detecting a memory access request requiring a variable number of data elements by a second internal bus master device (34) of the data processor (21); and keeping said control signal inactive and performing at least one external burst cycle to provide said variable number of data elements to said second internal bus master device (34) in response to a second memory access request signal and while said second memory access request signal is active.
Claim 10
Dependent Claim
40 words
The method of claim 9 further comprising the step of terminating said at least one external burst cycle by inactivating a control signal in response to said second internal bus master device (34) inactivating said second memory access request signal.
References Cited (Backward Citations)
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