Refresh period automatic detecting device for semiconductor memory device, method of automatically detecting refresh period, and refresh period output device

Claim 2

A refresh period automatic detecting device for a semiconductor memory device comprising: power-up detecting means for detecting power applied from a system; control means for producing a read/write timing control signal for internal data and at least one control signal to control overall components of the device in response to an output signal of the power-up detecting means; internal data generating means for producing internal data in response to the control signal; comparator means for comparing the internal data with internal data stored in a cell; and refresh circuit means for determining and storing a refresh period from the time relationship between the read/write timing control signal by the control signal of the control means if the two data do not correspond to each other.

Claim 3

A refresh period automatic detecting device for a semiconductor memory device according to claim 1, wherein the control means includes: self-test control means for producing control signal in response to the output signal of the power-up detecting means; clock generating means for producing clock signal in response to a control signal of the self-test control means; timer means for counting and outputting the clock signal in response to a control signal of the self-test control means; frequency dividing means for dividing the frequency of the clock signal through the timer means; address generating means for generating an internal column/row address by tuning an output signal of the frequency dividing means to the output signal of the timer means; read timing generating means producing a signal for reading out data in response to an output signal of each of the frequency dividing means and the address generating means; and write timing generating means receiving the output signal of each of the frequency dividing means and the address generating means.

Claim 4

A refresh period automatic detecting system for a semiconductor memory device according to claim 1, wherein the internal data generating means produces high-level data lower than the power supply voltage of the system, and low-level data higher than the ground voltage of the system.

Claim 5

A refresh period automatic detecting system for a semiconductor memory device according to claim 1, wherein the internal data generating means produces high-level data, which is the same as the power supply voltage of the system, and low-level data, which is the same as the ground voltage of the system.

Claim 6

A refresh period automatic detecting system for a semiconductor memory device according to claim 3, wherein the data generating means includes: a first resistor having one end connected to a power line; a second resistor serially connected to the other end of the first resistor; a third resistor serially connected to the second resistor; a first switch having both terminals connected to one and other ends of the first resistor, respectively; a second switch interposed between the second and third resistors; write driving means having one end connected between the first switch and one end of the second resistor, and the other end connected between the other end of the second switch and one end of the third resistor; and a third switch having both terminals connected between one end of the third resistor and the other end, wherein the first and third switches are turned on by the control signal of the control means during operation to find the refresh period, and after detecting the refresh period, the control signal of the control means is input as an inverted signal through an inverter to turn the second switch off.

Claim 7

A refresh period automatic detecting device for a semiconductor memory device according to claim 5, wherein the first and third resistors are each variable resistors.

Claim 8

A refresh period automatic detecting device for a semiconductor memory device according to claim 1, wherein a refresh period external output system includes: detecting means detecting a test mode in response to a given address signal applied from the outside; refresh test control means actuated by a detecting signal of the detecting means, and producing plural control signals for refresh test; a refresh circuit producing a signal in response to the refresh period stored in the refresh circuit means in response to one of the control signals; data output control means controlling data output in response to one of the control signals; and a data output circuit producing a signal in response to the refresh period by a control signal of the data output control means.

Claim 11

A method of automatically detecting a refresh period for a semiconductor memory device according to claim 8, comprising the steps: storing internal data if the two data correspond to each other; reading data out of the cell; and repeating the comparing step until the two data do not correspond to each other by changing a delay time of a timer means.

Claim 12

A method of automatically detecting a refresh period for a semiconductor memory device according to claim 8, wherein the internal high-level data is produced to be lower than the power supply voltage of the system and the low-level data is produced to be higher than the ground voltage of the system by the control signal.