Direct view infrared MEMS structure

Claim 2

A field emissive device formed on a semiconductor substrate having an upper surface and a lower surface and being composed of a substrate material, the field emissive device comprising: a plurality of emitters formed within a pixel region of the substrate, each emitter formed substantially of the substrate material, extending vertically from a base surface of the semiconductor substrate, and having a conical shape including a tip oriented upward; a deflectable conductive gate disposed above the pixel region and generally parallel to the upper surface, the conductive gate being anchored to the semiconductor substrate and including a bendable bi-material film including a conductive film and a further film, wherein the further film and the conductive film have respectively different thermal expansion coefficients.

Claim 3

The field emissive device as in claim 1, wherein the conductive gate is anchored to the semiconductor substrate by a thermal isolation support element.

Claim 4

The field emissive device as in claim 2, wherein the thermal isolation support element comprises silicon carbide.

Claim 5

The field emissive device as in claim 1, wherein the substrate material is transmissive to infrared radiation and the infrared radiation is incident upon the lower surface of the semiconductor substrate.

Claim 6

A field emissive device as in claim 1, wherein the deflectable conductive gate further includes an infrared radiation absorber material.

Claim 7

The field emissive device as in claim 5, wherein the infrared absorber material is disposed between the conductive film and the further film.

Claim 8

The field emissive device as in claim 5, wherein the infrared absorber material comprises TiW.

Claim 9

The field emissive device as in claim 1, wherein the further film comprises silicon carbide and the conductive film comprises gold.

Claim 10

The field emissive device as in claim 8, wherein the silicon carbide film acts as an infrared absorber material.

Claim 11

The field emissive device as in claim 1, wherein the deflectable conductive gate has a plurality of openings extending therethrough, each opening being disposed above a corresponding emitter of the plurality of emitters, and electrons emitted by the plurality of emitters are directed through the openings.

Claim 12

The field emissive device as in claim 10, further comprising a phosphor plate generally parallel with the upper surface of the semiconductor substrate and adapted for absorbing the electrons which are directed through the openings in the conductive gate to emit light.

Claim 13

The field emissive device as in claim 11, wherein the phosphor plate is connected to circuitry which provides an electrical bias to the phosphor plate which acts to accelerate the electrons which are directed through the openings in the conductive gate toward the phosphor plate.

Claim 14

The field emissive device as in claim 11, wherein the phosphor plate is spaced about 1000 microns above the upper surface of the semiconductor substrate.

Claim 15

The field emissive device as in claim 11, wherein the phosphor plate and the semiconductor substrate are mounted in a fixed configuration.

Claim 16

The field emissive device as in claim 1, wherein the deflectable conductive gate is spaced about 1 micron above the plurality of emitters.

Claim 17

The field emissive device as in claim 1, wherein the conductive gate and the plurality of emitters are electrically connected to circuitry which produces an electric field between the plurality of emitters and the gate.

Claim 18

The field emissive device as in claim 1, wherein the plurality of emitters comprises 10 to 200 emitters.

Claim 19

The field emissive device as in claim 1, wherein the substrate material comprises silicon, and the lower surface of the substrate is coated with an anti-reflective coating.

Claim 20

The field emissive device as in claim 1, wherein the conductive gate is generally rectangular and has a width within the range of 25 microns to 150 microns and a length within the range of 25 microns to 150 microns.

Claim 21

The field emissive device as in claim 1, further comprising a micro-cantilever arm connecting the conductive gate to the substrate, the arm having a width ranging from 3 microns to 6 microns and a length ranging from 40 microns to 400 microns.

Claim 22

The field emissive device as in claim 1, wherein the conductive gate is anchored to the semiconductor substrate by an electrically insulating, thermal isolation support element, and further comprises an interconnect film coupled to the conductive film and extending along the thermal isolation support element over and insulated from the substrate to connect with external circuitry.

Claim 23

The field emissive device as in claim 21, wherein the interconnect film comprises TiW.

Claim 24

The field emissive device as in claim 1, further comprising an infrared radiation transparent gate shield structure formed on the base surface of the semiconductor substrate between the emitters, the gate shield structure comprising a gate shield film disposed between upper and lower protective layers.

Claim 25

The field emissive device as in claim 23, wherein the upper and lower protective layers each comprise silicon carbide.

Claim 26

The field emissive device as in claim 23, wherein the gate shield film comprises one of a tin oxide film, an indium tin oxide film, and a doped polycrystalline silicon film.

Claim 27

The field emissive device as in claim 1, further comprising a boron nitride film disposed on the plurality of emitters.

Claim 28

The field emissive device as in claim 1, wherein the plurality of emitters have an average height within a range of 1 to 3 microns.

Claim 29

The field emissive device as in claim 1, further comprising an infrared radiation transparent gate shield structure formed on the base surface of the semiconductor substrate between the emitters, the gate shield structure comprising a gate shield film disposed over a lower protective layer formed of silicon carbide.

Claim 30

An infrared imager comprising an array of field emissive devices formed within a semiconductor substrate having an upper surface and composed of a substrate material, each field emissive device comprising: a plurality of emitters formed within a pixel region of the substrate, each emitter formed primarily of the substrate material, extending vertically from a base surface of the semiconductor substrate having a conical shape and including a tip oriented upward; and a deflectable conductive gate disposed above the pixel region and generally parallel to the upper surface, the conductive gate being anchored to the semiconductor substrate including a bendable bi-material film including a conductive film and a further film, the deflectable conductive gate further comprising a plurality of openings positioned above respective ones of the plurality of emitters.

Claim 31

An infrared imager comprising an array of field emissive devices formed within a semiconductor substrate having an upper surface and composed of a substrate material, each field emissive device comprising: a plurality of emitters formed within a pixel region of the substrate, each emitter formed primarily of the substrate material, extending vertically from a base surface of the semiconductor substrate having a conical shape and including a tip oriented upward; and a deflectable conductive gate disposed above the pixel region and generally parallel to the upper surface, the conductive gate being anchored to the semiconductor substrate including a bendable bi-material film including a conductive film and a further film, the deflectable conductive gate further comprising a plurality of openings positioned above respective ones of the plurality of emitters.

Claim 32

The infrared imager as in claim 29, wherein the conductive gate of each field emissive device includes an infrared radiation absorber material.

Claim 33

The infrared imager as in claim 29, wherein the conductive gate of each field emissive device is anchored to the semiconductor substrate by a thermal isolation support element and further comprises an interconnect film coupling each of the conductive gates to each other conductive gate.

Claim 34

The infrared imager as in claim 31, wherein the conductive gate of each field emissive device further includes an infrared radiation absorber material, and the interconnect film and the infrared absorber material each comprise TiW.

Claim 35

The infrared imager as in claim 29, further comprising a phosphor plate disposed above, and generally parallel to, the upper surface of the substrate, the phosphor sheet being adapted to absorb electrons emitted from emitters of the plurality of emitters for each field emissive device of the array of field emissive devices, to emit light.

Claim 36

The infrared imager as in claim 33, wherein the conductive gate of each field emissive device of the array of field emissive devices is electrically connected to circuitry which provides an electric field between the plurality of emitters and the conductive gate, and the phosphor plate is connected to further circuitry which provides an electrical bias to the phosphor plate which electrical bias acts to accelerate the electrons emitted by the field emissive devices toward the phosphor plate.

Claim 37

The infrared imager as in claim 29, wherein each field emissive device further comprises an infrared radiation transparent gate shield film structure disposed within the pixel region and on the base surface between the emitters of the plurality of emitters.

Claim 38

The infrared imager as in claim 35, further comprising a correction circuit adapted for individually applying an electric potential between the conductive gates and the gate shield film structure for each field emissive device of the array of field emissive devices.

Claim 39

The infrared imager as in claim 29, wherein the plurality of emitters of each field emissive device are coated with a boron nitride film.

Claim 40

A night vision system, comprising an array of field emissive devices formed within a semiconductor substrate having an upper surface and composed of a substrate material, each field emissive device comprising: a plurality of emitters formed within a pixel region of the substrate, each emitter formed primarily of the substrate material, extending vertically from a base surface, and having a conical shape including a tip oriented upward; and a deflectable conductive gate disposed above the pixel region and generally parallel to the upper surface, the conductive gate being anchored to the semiconductor substrate by a thermal isolation support element and including an infrared radiation absorber material and a bi-material film, the bi-material film being bendable and including a conductive film, and the deflectable conductive gate having a plurality of openings extending therethrough, each opening disposed above a corresponding emitter of the plurality of emitters, and the conductive gate including an electrical connection film which connects the gate electrically to circuitry which produces an electric field between the plurality of emitters and the conductive gate, and a phosphor plate disposed above, and generally parallel to, the upper surface, the phosphor sheet adapted to absorb electrons emitted by the emitter, and connected to further circuitry which provides an electrical bias to the phosphor plate to accelerate the electrons emitted by the emitter toward the phosphor plate, a housing containing at least the array, the phosphor plate, the circuitry, and the further circuitry, wherein the housing positions the semiconductor substrate so that a bottom surface thereof is oriented for receiving incident infrared radiation, and the substrate material is transmissive to infrared radiation.

Claim 41

A night vision system, comprising an array of field emissive devices formed within a semiconductor substrate having an upper surface and composed of a substrate material, each field emissive device comprising: a plurality of emitters formed within a pixel region of the substrate, each emitter formed primarily of the substrate material, extending vertically from a base surface, and having a conical shape including a tip oriented upward; and a deflectable conductive gate disposed above the pixel region and generally parallel to the upper surface, the conductive gate being anchored to the semiconductor substrate by a thermal isolation support element and including an infrared radiation absorber material and a bi-material film, the bi-material film being bendable and including a conductive film, and the deflectable conductive gate having a plurality of openings extending therethrough, each opening disposed above a corresponding emitter of the plurality of emitters, and the conductive gate including an electrical connection film which connects the gate electrically to circuitry which produces an electric field between the plurality of emitters and the conductive gate, and a phosphor plate disposed above, and generally parallel to, the upper surface, the phosphor sheet adapted to absorb electrons emitted by the emitter, and connected to further circuitry which provides an electrical bias to the phosphor plate to accelerate the electrons emitted by the emitter toward the phosphor plate, a housing containing at least the array, the phosphor plate, the circuitry, and the further circuitry, wherein the housing positions the semiconductor substrate so that a bottom surface thereof is oriented for receiving incident infrared radiation, and the substrate material is transmissive to infrared radiation.

Claim 42

The night vision system as in claim 38, wherein the housing comprises a hand-held unit.

Claim 43

The night vision system as in claim 38, wherein the housing comprises a unit shaped to be worn on a person's head.

Claim 44

The night vision system as in claim 38, wherein each field emissive device further comprises an infrared radiation transparent gate shield film structure disposed within the pixel region and on the base surface between the emitters of the plurality of emitters.

Claim 45

The night vision system as in claim 41, further comprising a correction circuit adapted for individually applying an electric potential between the conductive gate and the gate shield film structure for each field emissive device of the array of field emissive devices.

Claim 48

The method as in claim 43, wherein said step (a) includes the step of providing, in the pixel region of each field emissive device, a gate shield structure formed on a base surface between the emitters.

Claim 49

The method as in claim 45, further comprising the step (e) of individually applying an electric potential between the conductive gate and the corresponding gate shield structure for each field emissive device of the array of field emissive devices.

Claim 50

The method as in claim 45, further comprising the step of electrically biasing the phosphor plate to accelerate electrons emitted by the field emissive devices towards the phosphor plate.

Claim 51

A process for forming an infrared imager within a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate formed of an infrared transmissive substrate material and having an upper surface and a lower surface; (b) forming a plurality of emitters in close proximity to one another and defining a pixel region, each emitter formed within the upper surface, substantially of the substrate material, and having a generally conical shape including a tip oriented upward; and (c) forming a deflectable bi-material gate over the pixel region, the bi-material gate being anchored to the substrate, and including a plurality of openings therethrough, each opening superjacent to a respective emitter of the plurality of emitters.

Claim 52

A process for forming an infrared imager within a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate formed of an infrared transmissive substrate material and having an upper surface and a lower surface; (b) forming a plurality of emitters in close proximity to one another and defining a pixel region, each emitter formed within the upper surface, substantially of the substrate material, and having a generally conical shape including a tip oriented upward; and (c) forming a deflectable bi-material gate over the pixel region, the bi-material gate being anchored to the substrate, and including a plurality of openings therethrough, each opening superjacent to a respective emitter of the plurality of emitters.

Claim 53

The process as in claim 47, wherein step (b) comprises the steps of: (b1) forming a pattern of a masking material, the pattern including a plurality of generally circular dots arranged in close proximity to one another and defining a pixel region; (b2) isotropically etching the upper surface of the semiconductor substrate, thereby forming a generally conical emitter beneath each corresponding dot of the plurality of dots, and within the substrate, and a base surface generally parallel to the upper surface and extending between the emitters within the pixel region; and (b3) removing the masking material, and further comprising the step (b4) of oxidizing the substrate in a steam environment to form an oxide film on the substrate, the oxide film forming a release layer over the pixel region.

Claim 54

The process as in claim 48, wherein step (b4) comprises the step of thermally oxidizing the substrate.

Claim 55

The process as in claim 47, further comprising the step (b1) of oxidizing the substrate in a steam environment to form an oxide film on the substrate, the oxide film including a release layer over the pixel region, and wherein step (c) comprises the steps of: (c1) forming at least one anchor via extending through the oxide film and providing contact to the substrate; (c2) forming a thermal isolation material within the anchor via, over the pixel region, and extending between the anchor via and the pixel region, the thermal isolation material forming an anchor within the anchor via and a first bi-material film over the pixel region; (c3) forming a first plurality of openings through the first bi-material film, each opening being superjacent to an emitter of the plurality of emitters; (c4) forming a second bi-material film over the pixel region; (c5) forming a plurality of openings through the second bi-material film over corresponding openings of the first plurality of openings; and (c6) removing the release layer.

Claim 56

The process as in claim 50, further comprising the step (c2A) of forming an infrared absorber material over the thermal isolation material, and wherein step (c3) comprises forming a first plurality of holes through the first bi-material film and the infrared absorber material.

Claim 57

The process as in claim 51, wherein step (c2A) comprises forming a TiW film over the infrared absorber material.

Claim 58

The process as in claim 51, wherein the infrared absorber material is a conductive material and is patterned to serve as an interconnect connecting to the bi-material gate of the imager to external circuitry.

Claim 59

A process for forming an array of infrared imagers within a semiconductor device, each infrared imager formed according to the process as in claim 51.

Claim 60

The process as in claim 54, wherein the infrared absorber material is a conductive film, and further comprising step (d) of providing electrical connections among the bi-material gates of each infrared imager of the array of infrared imagers.

Claim 61

The process as in claim 50, wherein step (c2) comprises the step of forming a silicon carbide film.

Claim 62

The process as in claim 50, wherein step (c2) comprises the step of forming a thermal isolation material also serving as an infrared absorber material.

Claim 63

The process as in claim 50, wherein step (c4) comprises the step of forming a gold film over the pixel region.

Claim 64

The process as in claim 50, further comprising steps of: (b2) removing the oxide film; (b3) forming a boron-nitride film on the emitters of the plurality of emitters; and (b4) re-forming an oxide film by means of chemical vapor deposition, the oxide film including a further release layer over the pixel region, and wherein the step of removing the release layer comprises the step of removing the further release layer.

Claim 65

The process as in claim 50, further comprising forming an infrared transparent gate shield prior to the step of forming at least one anchor via using a process including steps: (b2) removing the oxide film: (b3) forming a base layer on a base surface extending between the emitters of the plurality of emitters defining the pixel region; (b4) forming a layer of one of tin oxide, indium tin oxide and doped polycrystalline silicon over the base layer; and (b5) forming an oxide film by one of coating and chemical vapor deposition, the oxide film forming a further release layer over the pixel region, and wherein the step of removing the release layer comprises removing the further release layer.

Claim 66

The process as in claim 60 further comprising step (b41) forming a cover layer over the layer of one of tin oxide, indium tin oxide, and doped polycrystalline silicon.

Claim 67

The process as in claim 61, wherein the steps of forming the base layer and the cover layer each comprise forming a silicon carbide film.

Claim 68

The process as in claim 47, further comprising the step (a1) of polishing the lower surface of the semiconductor substrate.

Claim 69

The process as in claim 47, further comprising the step (a1) of coating the lower surface of the semiconductor substrate with an anti-reflective coating.

Claim 70

The process as in claim 47, further comprising step (d) depositing a boron-nitride film on the emitters of the plurality of emitters.

Claim 71

The process as in claim 47, further comprising steps (d) affixing a phosphor plate above and substantially parallel to the upper surface, and (e) coupling a circuit to the substrate, the circuit providing an electric potential between the plurality of emitters and the bi-material gate to generate a localized electric field.

Claim 72

The process as in claim 66, further comprising step (f) coupling a further circuit to the substrate, the further circuit providing an electrical bias to the phosphor plate.

Claim 73

The process as in claim 47, in which step (b) includes forming a plurality of emitters having an average height within the range of 1-3 microns.