Patent US6134632A successfully refreshed from Google Patents.
US6134632A
Expired / Lapsed
US
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Controller that supports data merging utilizing a slice addressable memory array
Assignee: Intel Corp
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Filing: 1998-01-26
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Granted: 2000-10-17
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Expires: 2018-01-26
Abstract
Abstract A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.
Inventors
- 👤 Lily Pao Looi
- 👤 Sin Tan
- 👤 John Urbanski
- 👤 Christopher Van Beek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/0804; Y; Y10; Y10S; Y10S707/00; Y10S707/99941; Y10S707/99942
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
120 words
A method of merging first and second data sets from different sources in a slice addressable random-access memory array including an associated array of slice enable bits, said method comprising the steps of: enabling a row of the slice addressable random access memory array for writing; designating a slice of said row of the slice-addressable random access memory array enabled for writing by setting an associated bit in the associated array of slice enable bits; writing the first data set to the designated slice of said row of the slice addressable random access memory enabled for writing; and writing the second data set to previously undesignated slices of said row of the slice addressable random access memory enabled for writing.
Claim 2
Independent Claim
120 words
A method of merging first and second data sets from different sources in a slice addressable random-access memory array including an associated array of slice enable bits, said method comprising the steps of: enabling a row of the slice addressable random access memory array for writing; designating a slice of said row of the slice-addressable random access memory array enabled for writing by setting an associated bit in the associated array of slice enable bits; writing the first data set to the designated slice of said row of the slice addressable random access memory enabled for writing; and writing the second data set to previously undesignated slices of said row of the slice addressable random access memory enabled for writing.
Claim 3
Dependent Claim
10 words
The method of claim 1, wherein said slices are bytes.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said slice addressable memory array is a data buffer of a memory controller.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein said associated array of slice enable bits is a vector.
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein said associated array of slice enable bits has the same number of rows as said slice addressable random access memory array.
Claim 7
Dependent Claim
29 words
The method of claim 1, wherein said associated array of slice enable bits has the same number of columns as said slice addressable random access memory array has slices.
Claim 8
Dependent Claim
39 words
The method of claim 1, wherein said associated array of slice enable bits has the same number of rows as said slice addressable memory array and the same number of columns as said slice addressable memory array has slices.
Claim 9
Independent Claim
153 words
A method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory write operation, said computer system including a slice addressable random access memory buffer comprised of at least one word line corresponding to a cache line, and an array of slice enable bits associated with slices of the word line of the slice addressable random access memory buffer, said method comprising the steps of: setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to the slices of said word line associated with said set slice enable bits in said slice addressable random access memory buffer; and write merging data from the modified cache line to the slices of said word line not associated with said set slice enable bits in said slice addressable random access memory buffer.
Claim 10
Independent Claim
153 words
A method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory write operation, said computer system including a slice addressable random access memory buffer comprised of at least one word line corresponding to a cache line, and an array of slice enable bits associated with slices of the word line of the slice addressable random access memory buffer, said method comprising the steps of: setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to the slices of said word line associated with said set slice enable bits in said slice addressable random access memory buffer; and write merging data from the modified cache line to the slices of said word line not associated with said set slice enable bits in said slice addressable random access memory buffer.
Claim 11
Dependent Claim
143 words
A data buffer in a memory controller of a computer system including a processor, a processor bus, and a memory subsystem, said data buffer comprising: a slice addressable random access memory array having a plurality of word lines comprised of slices; a memory bus configured for communication between said slice addressable random access memory array and said memory subsystem; a first interface coupled between said slice addressable random access memory array and said processor bus, said first interface including a plurality of individually enabled-data paths configured for data communication with said slices of said slice addressable random access memory array and a second interface coupled between said slice addressable random access memory array and an input/output bus said second interface including a plurality of individually enabled data paths configured for data communication with said slices of said slice addressable random access memory array.
Claim 12
Dependent Claim
143 words
A data buffer in a memory controller of a computer system including a processor, a processor bus, and a memory subsystem, said data buffer comprising: a slice addressable random access memory array having a plurality of word lines comprised of slices; a memory bus configured for communication between said slice addressable random access memory array and said memory subsystem; a first interface coupled between said slice addressable random access memory array and said processor bus, said first interface including a plurality of individually enabled-data paths configured for data communication with said slices of said slice addressable random access memory array and a second interface coupled between said slice addressable random access memory array and an input/output bus said second interface including a plurality of individually enabled data paths configured for data communication with said slices of said slice addressable random access memory array.
Claim 13
Dependent Claim
15 words
The data buffer of claim 9, wherein said slice addressable random access memory is multi-ported.
Claim 14
Dependent Claim
50 words
The data buffer of claim 10, further comprising: a third interface coupled between said slice addressable random access memory array and another input/output bus, said third interface including a plurality of individually enabled data paths configured for data communication with said slices of said slice addressable random access memory array.
Claim 15
Dependent Claim
21 words
The data buffer of claim 9, wherein said slice addressable random access memory array is comprised of static random access memory.
Claim 16
Dependent Claim
51 words
The data buffer of claim 10, further comprising an address decoder operably coupled to said slice addressable random access memory array, said processor bus, and said input/output bus for coupling a word line enable to said slice addressable random access memory array responsive to said processor bus and said input/output bus.
Claim 17
Dependent Claim
53 words
The data buffer of claim 9, wherein said memory controller further comprises an array of slice enables operably coupled to said first interface such that said first interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enables.
Claim 18
Dependent Claim
44 words
The data buffer of claim 14, wherein said slice enables are bits and said first interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enable bit being set.
Claim 19
Dependent Claim
44 words
The data buffer of claim 14, wherein said slice enables are bits and said first interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enable bit being reset.
Claim 20
Dependent Claim
53 words
The data buffer of claim 10, wherein said memory controller further comprises an array of slice enables operably coupled to said second interface such that said second interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enables.
Claim 21
Dependent Claim
136 words
A computer system, comprising: a host memory; a plurality of agents; a memory controller operatively connected to said plurality of agents, via a system bus and/or an input/output bus, operatively connected to said host memory, via a memory bus, and configured to perform data merging to preserve cache coherency, said memory controller comprising: a slice addressable random access memory array having multiple input/output ports and a plurality of word lines comprised of slices; a first interface provided to interface said slice addressable random access memory array with said system bus for data communication with said slices of said slice addressable random access memory array; and a second interface provided to interface said slice addressable random access memory array with said input/output bus for data communication with said slices of said slice addressable random access memory array.
Claim 22
Dependent Claim
136 words
A computer system, comprising: a host memory; a plurality of agents; a memory controller operatively connected to said plurality of agents, via a system bus and/or an input/output bus, operatively connected to said host memory, via a memory bus, and configured to perform data merging to preserve cache coherency, said memory controller comprising: a slice addressable random access memory array having multiple input/output ports and a plurality of word lines comprised of slices; a first interface provided to interface said slice addressable random access memory array with said system bus for data communication with said slices of said slice addressable random access memory array; and a second interface provided to interface said slice addressable random access memory array with said input/output bus for data communication with said slices of said slice addressable random access memory array.
Claim 23
Dependent Claim
43 words
The computer system of claim 18, wherein said memory controller further comprises a third interface provided to interface said slice addressable random access memory array with another input/output bus for data communication with said slices of said slice addressable random access memory array.
Claim 24
Dependent Claim
21 words
The computer system of claim 19, wherein said slice addressable random access memory array is comprised of static random access memory.
Claim 25
Dependent Claim
55 words
The computer system of claim 19, wherein said memory controller further comprises an address decoder operably coupled to said slice addressable random access memory array, said system bus and said input/output bus, for coupling a word line enable to said slice addressable random access memory array responsive to said system bus and said input/output bus.
Claim 26
Dependent Claim
53 words
The computer system of claim 19, wherein said memory controller further comprises an array of slice enables operably coupled to said first interface such that said first interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enables.
Claim 27
Dependent Claim
44 words
The computer system of claim 22, wherein said slice enables are bits and said first interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enable bit being set.
Claim 28
Dependent Claim
53 words
The computer system of claim 19, wherein said memory controller further comprises an array of slice enables operably coupled to said second interface such that said second interface individually enables a data path configured for data communication with a slice of said slice addressable random access memory array responsive to said slice enables.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |