Patent US6134181A successfully refreshed from Google Patents.
US6134181A
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Configurable memory block
Assignee: Micron Technology Inc
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Filing: 1999-02-24
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Granted: 2000-10-17
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Expires: 2019-02-24
Abstract
Abstract A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.
Inventors
- 👤 Greg J. Landry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:33
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
80 words
A circuit comprising: a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals; a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and an output circuit configured to present an output having a variable word-width in response to said control signal.
Claim 2
Dependent Claim
80 words
A circuit comprising: a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals; a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and an output circuit configured to present an output having a variable word-width in response to said control signal.
Claim 3
Dependent Claim
47 words
The circuit according to claim 1, wherein said output circuit is further configured to present either a synchronous or an asynchronous output in response to (i) said clock signal, (ii) said control signal and (iii) data read from one or more of said plurality of storage elements.
Claim 4
Dependent Claim
34 words
The circuit according to claim 1, further comprising: an address transition detect circuit configured to precharge a number of bitlines in response to a transition of one of said plurality of internal address signals.
Claim 5
Dependent Claim
35 words
The circuit according to claim 1, further comprising a plurality of bitline loads, each connected to one of a plurality of bitline pairs, wherein said bitline loads reduce the DC power consumed by the circuit.
Claim 6
Dependent Claim
15 words
The circuit according to claim 4, wherein each of said bitline loads comprises a half-latch.
Claim 7
Dependent Claim
20 words
The circuit according to claim 4, wherein each of said bitline loads comprises a first and a second cross-coupled gate.
Claim 8
Dependent Claim
25 words
The circuit according to claim 4, wherein each of said bitline loads comprises (i) a half-latch and (ii) a first and a second cross-coupled gate.
Claim 9
Dependent Claim
19 words
The circuit according to claim 4, wherein said bitline loads reduce the DC power to a zero standby current.
Claim 10
Dependent Claim
14 words
The circuit according to claim 4, wherein said bitlines have a full rail switching.
Claim 11
Dependent Claim
13 words
The circuit according to claim 1, wherein said circuit comprises an embedded memory.
Claim 12
Dependent Claim
21 words
The circuit according to claim 4, further comprising a plurality of data buffers each connected to one of said bitline pairs.
Claim 13
Dependent Claim
26 words
The circuit according to claim 4, further comprising a plurality of data line equalization circuits each coupled to one of a number of data line pairs.
Claim 14
Dependent Claim
30 words
The circuit according to claim 12, further comprising a data output circuit configured to present a data output in response to said first and second outputs of a data buffer.
Claim 15
Dependent Claim
30 words
The circuit according to claim 1, wherein said circuit operates as a random access memory (RAM), read only memory (ROM) or a logic circuit, in response to said control signal.
Claim 16
Dependent Claim
38 words
The circuit according to claim 1, wherein said circuit further comprises a plurality of bitline loads, an equalization circuit, a data buffer circuit, a data line equalization circuit and a data output circuit, each fabricated using CMOS transistors.
Claim 17
Dependent Claim
68 words
A circuit comprising: means for storing data in a plurality of storage elements in response to one of a plurality of internal address signals; means for generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and means for generating an output having a variable wordwidth in response to said control signal.
Claim 18
Dependent Claim
68 words
A circuit comprising: means for storing data in a plurality of storage elements in response to one of a plurality of internal address signals; means for generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and means for generating an output having a variable wordwidth in response to said control signal.
Claim 19
Independent Claim
80 words
A method for reading and writing data to a plurality of storage elements comprising the steps of: (A) configuring each of said storage elements to store data in response to one of a plurality of internal address signals; (B) generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and (C) generating an output having a variable word-width in response to said control signal.
Claim 20
Independent Claim
80 words
A method for reading and writing data to a plurality of storage elements comprising the steps of: (A) configuring each of said storage elements to store data in response to one of a plurality of internal address signals; (B) generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and (C) generating an output having a variable word-width in response to said control signal.
Claim 21
Dependent Claim
29 words
The method according to claim 17, further comprising the step of: (D) precharging a number of bitlines in response to a transition of one of said internal address signals.
Claim 22
Dependent Claim
35 words
The method according to claim 17, wherein said plurality of storage elements can be configured as a random access memory (RAM), read only memory (ROM) or a logic circuit, in response to said control signal.
Claim 23
Independent Claim
88 words
An apparatus comprising: a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals; a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and an address transition detect circuit configured to precharge a number of bitlines in response to a transition of one of said plurality of internal address signals.
Claim 24
Independent Claim
88 words
An apparatus comprising: a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals; a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and an address transition detect circuit configured to precharge a number of bitlines in response to a transition of one of said plurality of internal address signals.
References Cited (Backward Citations)
US5384745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |