High data rate write process for non-volatile flash memories

Claim 2

A non-volatile semiconductor memory comprising: a plurality of write pipelines, each write pipeline comprising: an array of non-volatile memory cells; and a write circuit coupled to the array, wherein when stated on a programming operation for a selected memory cell in the aray, the write circuit applies a first voltage to the selected memory cell to drive a current through the selected memory cell; a timing circuit coupled to sequentially start programming operations by the write circuits, wherein a second of the programming operations on a second selected memory cell begins before a first of the programming operations on a first selected memory cell is complete; and a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming operations.

Claim 3

The memory of claim 1, wherein the memory is a binary memory.

Claim 4

The memory of claim 1, wherein the memory is a multiple-bits-per-cell memory.

Claim 5

The memory of claim 1, wherein the memory is an analog memory.

Claim 6

The memory of claim 1, wherein in each write pipeline, the write circuit applies the first voltage to a floating gate transistor in the selected memory cell to change a threshold voltage of the floating gate transistor during the programming operation.

Claim 7

The memory of claim 5, wherein in each write pipeline, the write circuit applies the first voltage to the floating gate transistor in the selected memory cell to induce channel hot electron injection in the selected memory cell during the programming operation.

Claim 8

The memory of claim 5, wherein in each write pipeline, the write circuit applies a second voltage to the floating gate transistor in the selected memory cell to determine whether the threshold voltage has reached a target threshold voltage.

Claim 9

A non-volatile semiconductor memory comprising: a plurality of write pipelines, each write pipeline comprising: an array of non-volatile memory cells; and a write circuit coupled to the array, wherein each write circuit comprises: a column decoder coupled to column lines in the array, wherein during a programming operation, the column decoder selects a column line that is coupled to a selected memory cell; a selection circuit coupled to the column decoder, wherein the selection circuit selects a voltage that the column decoder applies to the selected column line, the selection circuit alternating between selecting a first voltage and selecting a second voltage, wherein when started on a programming operation for the selected memory cell in the array, the write circuit applies the first voltage to a floating gate transistor in the selected memory cell to drive a current through the selected memory cell and change a threshold voltage of the floating gate transistor and applies the second voltage to the floating gate transistor in the selected memory cell to determine whether the threshold voltage has reached a target threshold voltage; and a sense amplifier circuit coupled to the column decoder, wherein the column decoder connects the sense amplifier circuit to the selected column line when the selection circuit selects the second voltage and disconnects the sense amplifier from the selected column line when the selection circuit selects the first voltage; a timing circuit coupled to sequentially start programming operations by the write circuits, wherein a programming operation on a second selected memory cell begins before a programming operation on a first selected memory cell is complete; and a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming operations.

Claim 10

A non-volatile semiconductor memory comprising: a plurality of write pipelines, each write pipeline comprising: an array of non-volatile memory cells; and a write circuit coupled to the array, wherein each write circuit comprises: a column decoder coupled to column lines in the array, wherein during a programming operation, the column decoder selects a column line that is coupled to a selected memory cell; a selection circuit coupled to the column decoder, wherein the selection circuit selects a voltage that the column decoder applies to the selected column line, the selection circuit alternating between selecting a first voltage and selecting a second voltage, wherein when started on a programming operation for the selected memory cell in the array, the write circuit applies the first voltage to a floating gate transistor in the selected memory cell to drive a current through the selected memory cell and change a threshold voltage of the floating gate transistor and applies the second voltage to the floating gate transistor in the selected memory cell to determine whether the threshold voltage has reached a target threshold voltage; and a sense amplifier circuit coupled to the column decoder, wherein the column decoder connects the sense amplifier circuit to the selected column line when the selection circuit selects the second voltage and disconnects the sense amplifier from the selected column line when the selection circuit selects the first voltage; a timing circuit coupled to sequentially start programming operations by the write circuits, wherein a programming operation on a second selected memory cell begins before a programming operation on a first selected memory cell is complete; and a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming operations.

Claim 11

The memory of claim 8, wherein the write pipelines comprise: a plurality of odd numbered pipelines; and a plurality of even numbered pipelines, wherein when an odd numbered pipeline and an even numbered pipeline are both performing programming operations, the selection circuit in the odd numbered pipeline selects the first voltage when the selection circuit in the even numbered pipeline selects the second voltage and the selection circuit in the odd numbered pipeline selects the second voltage when the selection circuit in the even numbered pipeline selects the first voltage.

Claim 12

The memory of claim 1, further comprising a voltage regulator that controls an output signal from the charge pump to maintain the output signal at the first voltage.

Claim 13

A non-volatile semiconductor memory comprising: a plurality of banks of write pipelines, each write pipeline comprising: an array of non-volatile memory cells; and a write circuit coupled to the array, wherein: during a programming cycle for a selected memory cell in the array, the write circuit applies a first voltage to drive a current through the selected memory cell and change the threshold voltage of the selected memory cell; and during a verify cycle for the selected memory cell, the write circuit determines whether a threshold voltage of the selected memory cell has reached a target level representing a value being written into the selected memory cell; a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming cycles of the write circuits; and a timing circuit coupled to start programming cycles for overlapping write operations in the pipelines, wherein the timing circuit starts programming cycles for each bank at times that are different from when programming cycles start in the other banks.

Claim 14

A non-volatile semiconductor memory comprising: a plurality of banks of write pipelines, each write pipeline comprising: an array of non-volatile memory cells; and a write circuit coupled to the array, wherein: during a programming cycle for a selected memory cell in the array, the write circuit applies a first voltage to drive a current through the selected memory cell and change the threshold voltage of the selected memory cell; and during a verify cycle for the selected memory cell, the write circuit determines whether a threshold voltage of the selected memory cell has reached a target level representing a value being written into the selected memory cell; a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming cycles of the write circuits; and a timing circuit coupled to start programming cycles for overlapping write operations in the pipelines, wherein the timing circuit starts programming cycles for each bank at times that are different from when programming cycles start in the other banks.

Claim 15

The memory of claim 11, wherein the plurality of banks comprises a first bank and a second bank, and the timing circuit starts programming cycles in the first bank when verify cycles start in the second bank.

Claim 16

The memory of claim 11, wherein in each pipeline, writing the value to the selected cell requires a programming operation that includes a plurality of programming cycles and verify cycles; and the timing circuit sequentially starts programming operations by the pipelines in the banks.

Claim 17

The memory of claim 11, wherein each write circuit comprises: a column decoder coupled to column lines in the array, wherein during the programming cycles and the verify cycles, the column decoder selects a selected column line that is coupled to the selected memory cell; a selection circuit coupled to the column decoder, wherein the selection circuit selects a voltage that the column decoder applies to the selected column line, the selection circuit selects the first voltage for programming cycles and selects a second voltage for the verify cycles; and a sense amplifier circuit coupled to the column decoder, wherein the column decoder connects the sense amplifier circuit to the selected column line when the selection circuit selects the second voltage and disconnects the sense amplifier from the selected column line when the selection circuit selects the first voltage.

Claim 20

The method of claim 15, wherein: the first programming operation comprises keeping the charge pump coupled to drive the current through the first selected memory cell for a fixed time; and the second programming operation comprises keeping the charge pump coupled to drive the current through the second selected memory cell for the fixed time.

Claim 21

The method of claim 16, wherein the fixed time is sufficiently long that the programming operation changes a threshold voltage of a memory cell from a level representing a first binary level to a level representing a second binary value.

Claim 22

The method of claim 15, wherein: the first programming operation comprises: keeping the charge pump coupled to drive the current through the first selected memory cell during a first set of intervals; and determining during each of a second set of intervals whether the threshold voltage in the first selected memory cell has reached a first target level, each interval in the second set being separated from other intervals in the second set by one of the intervals in the first set; and the second programming operation comprises: keeping the charge pump coupled to drive the current through the second selected memory cell during an interval in the second set; and during an interval in the first set, determining whether the threshold voltage in the second selected memory cell has reached a second target level.