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US6133603A
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US
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Memory device and memory array
Assignee: Sony Corp
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Filing: 1998-12-08
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Granted: 2000-10-17
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Expires: 2018-12-08
Abstract
Abstract It is made possible to conduct writing and erasing information at high speed and with a low gate voltage, attain high integration with reduced power dissipation, and retain information accurately. It is also made possible to change the conductivity of a conduction layer efficiently depending on whether there are accumulated charges or not, even if the device is made finer. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. In the conduction layer, one insulation portion and one insulation portion allowing charge tunneling are formed with the barrier layer in between. The capacitance of the insulation portions is made smaller than e 2 /k B T (where e is the electric prime quantity, k B is the Boltzmann's constant, and T is operation temperature). The conduction layer, the transition layers, and the charge accumulation layer are made of Si. The barrier layers are made of SiO 2 so that the electron affinity is made large, and small alternately.
Inventors
- 👤 Kazumasa Nomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10D30/6891; H10D30/80; H10D30/801; H10D30/803; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A memory device comprising: a conduction layer having a plurality of insulation portions allowing charge tunneling; a charge accumulation layer for accumulating charges transferred from the conduction layer; one or more transition layers for transferring charges from the conduction layer to the charge accumulation layer and the conduction layer; and a plurality of barrier portions allowing charge tunneling, being respectively formed between one of the transition layers and the conduction layer, in between the transition layers, and between one of the transition layers and the charge accumulation layer, wherein, each of the insulation portions of the conduction layer has a capacitance smaller than e 2 /k B T, where e is the electric prime quantity, k B is the Boltzman's constant, and T is operation temperature.
Claim 2
Dependent Claim
126 words
A memory device comprising: a conduction layer having a plurality of insulation portions allowing charge tunneling; a charge accumulation layer for accumulating charges transferred from the conduction layer; one or more transition layers for transferring charges from the conduction layer to the charge accumulation layer and the conduction layer; and a plurality of barrier portions allowing charge tunneling, being respectively formed between one of the transition layers and the conduction layer, in between the transition layers, and between one of the transition layers and the charge accumulation layer, wherein, each of the insulation portions of the conduction layer has a capacitance smaller than e 2 /k B T, where e is the electric prime quantity, k B is the Boltzman's constant, and T is operation temperature.
Claim 3
Dependent Claim
41 words
A memory device according to claim 1, wherein each of the barrier portions has a capacitance smaller than e 2 /k B T, where e is the electric prime quantity, k B is the Boltzmann's constant, and T is operation temperature.
Claim 4
Dependent Claim
152 words
A memory device according to claim 1, wherein the conduction layer, the transition layers, and the charge accumulation layer are respectively made of a semiconductor; the barrier portion located between the conduction layer and the transition layer has a barrier layer made of a semiconductor which is smaller in electron affinity or larger in work function than the semiconductor of the conduction layer and the semiconductor of the transition layer; the barrier portion located between the transition layers has a barrier layer made of a semiconductor which is smaller in electron affinity or larger in work function than the semiconductors of the transition layers; and the barrier portion located between the transition layer and the charge accumulation layer has a barrier layer made of a semiconductor which is smaller in electron affinity or larger in work function than the semiconductor of the transition layer and the semiconductor of the charge accumulation layer.
Claim 5
Dependent Claim
46 words
A memory device according to claim 3, wherein the conduction layer, the transition layers, and the charge accumulation layer is respectively made of Si; and the barrier layers serving as barrier portions are respectively made of SiO 2 , Si 3 N 4 , or SiON.
Claim 6
Dependent Claim
51 words
A memory device according to claim 3, wherein the conduction layer, the transition layers, and the charge accumulation layer are respectively made of SiGe and Ge; and each of the barrier layers serving as barrier portions is made of SiGe, Si, SiO 2 , Si 3 N 4 , or SiON.
Claim 7
Dependent Claim
99 words
A memory device according to claim 3, wherein the conduction layer, the transition layers, and the charge accumulation layer are respectively made of a Group III-V compound semiconductor including at least one element selected from the group consisting of In and Ga of the Group III element and As of the Group V element; and each of the barrier layers serving as barrier portions is made of a Group III-V compound semiconductor including at least one element selected from the group consisting of In, Al and Ga of the Group III element and As of the Group V element.
Claim 8
Dependent Claim
99 words
A memory device according to claim 3, wherein the conduction layer, the transition layer, and the charge accumulation layer are respectively made of a Group III-V compound semiconductor including at least one element selected from the group consisting of In and Ga of the Group III element and Sb of the Group V element; and each of the barrier layers serving as barrier portions is made of a Group III-V compound semiconductor including at least one element selected from the group consisting of In, Al and Ga of the Group III element and Sb of the Group V element.
Claim 9
Dependent Claim
44 words
A memory device according to claim 1, wherein the conduction layer is made of a semiconductor; the transition layers and the charge accumulation layer are made of metal; and each of the barrier portions is formed by a barrier layer made of an insulator.
Claim 10
Dependent Claim
39 words
A memory device according to claim 8, wherein the transition layer and the charge accumulation layer are respectively made of Al; and each of the barrier layers serving as barrier portions is made of Al 2 O 3 .
Claim 11
Dependent Claim
61 words
A memory device according to claim 1, wherein the conduction layer is made of metal; each of the insulation portions of the conduction layer is formed by an insulation layer made of an insulator; the transition layers and the charge accumulation layer are made of metal; each of the barrier portions is formed by a barrier layer made of an insulator.
Claim 12
Dependent Claim
46 words
A memory device according to claim 10, wherein the conduction layer, the transition layers, and the charge accumulation layer are respectively made of Al; and each of the insulation layers serving as insulation portions of the conduction layer is made of Al 2 O 3 .
Claim 13
Dependent Claim
139 words
A memory array formed by integrating a plurality of memory devices, each of the memory devices comprising: a conduction layer having a plurality of insulation portions allowing charge tunneling; a charge accumulation layer for accumulating charges transferred from the conduction layer; one or more transition layers for transferring charges from the conduction layer to the charge accumulation layer and the conduction layer; and a plurality of barrier portions allowing charge tunneling, being respectively formed between one of the transition layers and the conduction layer, in between the transition layers, and between one of the transition layers and the charge accumulation layer, wherein, each of the insulation portions of the conduction layer has a capacitance smaller than e 2 /k B T, where e is the electric prime quantity, k B is the Boltzman's constant, and T is operation temperature.
Claim 14
Dependent Claim
139 words
A memory array formed by integrating a plurality of memory devices, each of the memory devices comprising: a conduction layer having a plurality of insulation portions allowing charge tunneling; a charge accumulation layer for accumulating charges transferred from the conduction layer; one or more transition layers for transferring charges from the conduction layer to the charge accumulation layer and the conduction layer; and a plurality of barrier portions allowing charge tunneling, being respectively formed between one of the transition layers and the conduction layer, in between the transition layers, and between one of the transition layers and the charge accumulation layer, wherein, each of the insulation portions of the conduction layer has a capacitance smaller than e 2 /k B T, where e is the electric prime quantity, k B is the Boltzman's constant, and T is operation temperature.
References Cited (Backward Citations)
US5463235A
Cited
US5604357A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |