US6127874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Skew adjustable IC and a method for designing the same
Assignee: Toshiba Corp
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Filing: 1997-09-29
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Granted: 2000-10-03
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Expires: 2017-09-29
Abstract
Abstract The present invention provides a semiconductor IC and a method for designing the same which adjusts the clock skews on a chip without additional delay circuit. A decrease in design time is realized when the semiconductor IC includes hard megacells (whose functions have been confirmed) or standard cell blocks. In the case of a semiconductor IC including hard megacells and a standard cell blocks, each megacell and standard cell block according to the present invention has sub-clock buffers on every row, for example, sub-clock buffers on the row and sub-clock buffers on the row in the megacell. The adjustment needed for accommodating clock skews on a chip is determined by calculating a delay time for the various IC chip blocks. Next, sub-clock buffers are chosen based on a result of a calculation for the delay time. Finally, the wiring design is completed which minimizes clock skew.
Inventors
- 👤 Shigemichi Wakabayashi
- 👤 Toshiyuki Oshima
- 👤 Osamu Fuji
- 👤 Shoichi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:26
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
66 words
A hard megacell for use in a semiconductor integrated circuit, the hard megacell comprising: a clock input node for receiving a system clock of the semiconductor integrated circuit; and a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of the system clock, each of the buffers being for selective connection to the clock input node.
Claim 2
Dependent Claim
66 words
A hard megacell for use in a semiconductor integrated circuit, the hard megacell comprising: a clock input node for receiving a system clock of the semiconductor integrated circuit; and a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of the system clock, each of the buffers being for selective connection to the clock input node.
Claim 3
Dependent Claim
24 words
The hard megacell of claim 1, wherein each of the buffers is selectively connected to either the clock input node or a fixed potential.
Claim 4
Dependent Claim
13 words
The hard megacell of claim 1, wherein the hard megacell is a CPU.
Claim 5
Independent Claim
71 words
A method for designing a semiconductor integrated circuit, the method comprising the steps of: choosing a hard megacell having a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of a system clock of the semiconductor integrated circuit; selecting at least one of the buffers; and connecting each of the buffers selected in the step of selecting to the system clock.
Claim 6
Independent Claim
71 words
A method for designing a semiconductor integrated circuit, the method comprising the steps of: choosing a hard megacell having a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of a system clock of the semiconductor integrated circuit; selecting at least one of the buffers; and connecting each of the buffers selected in the step of selecting to the system clock.
Claim 7
Dependent Claim
26 words
The method of claim 4, further including the step of connecting each of the buffers not selected in the step of selecting to a fixed potential.
Claim 8
Dependent Claim
29 words
The method of claim 4, wherein the step of selecting includes selecting the buffers based on a characteristic of a system clock wiring line for carrying the system clock.
Claim 9
Dependent Claim
24 words
The method of claim 6, wherein the step of selecting includes selecting the buffers based on a resistance of the system clock wiring line.
Claim 10
Dependent Claim
25 words
The method of claim 4, wherein the step of selecting includes selecting a number of the buffers less than a total number of the buffers.
Claim 11
Dependent Claim
30 words
The method of claim 4, wherein the buffers in the rows of elements of the hard megacell chosen by the step of choosing are selectively connected to the system clock.
Claim 12
Independent Claim
126 words
A method for designing a semiconductor integrated circuit, the method comprising the steps of: choosing a hard megacell having a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of a system clock of the semiconductor integrated circuit; measuring a wiring resistance between a clock input node of the hard megacell and a clock input node of one of the rows; determining a skew of the system clock based on the wiring resistance and a total number of cells in the one of the rows; determining a number of the buffers for minimizing the skew of the system clock; and connecting the number of the buffers determined in the step of determining to the system clock.
Claim 13
Independent Claim
126 words
A method for designing a semiconductor integrated circuit, the method comprising the steps of: choosing a hard megacell having a plurality of rows of elements, each of the rows further including at least one buffer for adjusting a skew of a system clock of the semiconductor integrated circuit; measuring a wiring resistance between a clock input node of the hard megacell and a clock input node of one of the rows; determining a skew of the system clock based on the wiring resistance and a total number of cells in the one of the rows; determining a number of the buffers for minimizing the skew of the system clock; and connecting the number of the buffers determined in the step of determining to the system clock.
Claim 14
Dependent Claim
23 words
The method of claim 10, further including the step of connecting each of a remaining number of the buffers to a fixed potential.
Claim 15
Dependent Claim
30 words
The method of claim 10, wherein the buffers in the rows of elements of the hard megacell chosen by the step of choosing are selectively connected to the system clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-03 | 2004-04-03 | 2004-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-03 | 2008-04-03 | 2008-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-03 | 2012-04-03 | 2012-10-03 | $7700.00 | Window Closed / Lapsed |