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US6125155A
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Broad-band digital filtering method and a filter implementing the method
Assignee: Alcatel Espace Industries SA
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Filing: 1996-10-18
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Granted: 2000-09-26
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Expires: 2016-10-18
Abstract
Abstract A digital filter method comprising the following steps: input signal data x(n) is sampled at sampling frequency Fe and shared between and stored in Q memories of shift register of FIFO type associated with the Q branches of the filter. The filter coefficients g m (p) are stored in at least one other memory referred to as a "coefficient" memory. Interpolation by L followed by decimation by M makes it possible to reduce the working frequency of the filter to the output frequency Fs=(L/M)Fe with L/M<1. Data samples x(n) are multiplied by the coefficients g m (p) at the rate Fs. According to the invention, the data samples x(n) in each branch remain present for a plurality of multiplications ≈Fe/Q, and the coefficients are rotated in each branch by address permutation in the coefficient memory at each clock period. The invention proposes various devices implementing the method. Applications in radar and in telecommunications.
Inventors
- 👤 Chantal Lesthievent
- 👤 Patrick Oudart
- 👤 Claudine Flament
- 👤 Eric Belis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:16
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0248; H03H17/0264; H03H17/0273; H03H17/0275; H03H17/06; H03H17/0621; H03H17/0635; H03H17/0685
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
123 words
A digital filter method comprising the following steps: input signal data x(n) is sampled at the input sampling frequency Fe and is shared between and stored in a plurality of Q memories of shift register or FIFO type, respectively associated with the Q branches of the filter; the filter coefficients g m (p) are stored in at least one other memory referred to as a "coefficient" memory; interpolation by L is performed on each branch; said data samples x(n) are multiplied by the said coefficients g m (p) at the rate of the output frequency Fs; and decimation by M, enabling the working frequency of the filter to be lowered to the output frequency Fs=(L/M)Fe, where L and M are integers and L/M<1.
Claim 2
Dependent Claim
123 words
A digital filter method comprising the following steps: input signal data x(n) is sampled at the input sampling frequency Fe and is shared between and stored in a plurality of Q memories of shift register or FIFO type, respectively associated with the Q branches of the filter; the filter coefficients g m (p) are stored in at least one other memory referred to as a "coefficient" memory; interpolation by L is performed on each branch; said data samples x(n) are multiplied by the said coefficients g m (p) at the rate of the output frequency Fs; and decimation by M, enabling the working frequency of the filter to be lowered to the output frequency Fs=(L/M)Fe, where L and M are integers and L/M<1.
Claim 3
Dependent Claim
41 words
A method according to claim 1, wherein said data samples x(n) in each branch remain present for a plurality ≈Fe/Q of multiplications and coefficients are rotated in each branch by permutation of addresses in said coefficient memory at each clock period.
Claim 4
Dependent Claim
59 words
A method according to claim 1, wherein said multiplications are performed in parallel on a plurality p of filter planes, each filter plane having Q branches, said p filter planes being connected in a parallel architecture, thereby enabling the working frequency of the filter to be lowered to the output frequency Fs=(L/pM)Fe with synchronous sequencing between the parallel filters.
Claim 5
Dependent Claim
55 words
A method according to claim 3, wherein said multiplications are formed in cascade by a plurality k of parallel filters, each parallel filter comprising p planes, said parallel filters being connected in series, the p outputs from each preceding parallel filter being connected to the p inputs of each following parallel filter in the cascade.
Claim 6
Dependent Claim
139 words
Digital filter architecture comprising: means for sharing input sampled data x(n); means for temporary storage of said input data x(n), e.g. a plurality Q of memories of shift register or FIFO type; Q branches of the filter; at least one other memory referred to as a "coefficient" memory for storing filter coefficients g m (p); means for multiplying data x(n) by the coefficients g m (p); means for performing interpolation by L; means for decimation by M, with integer L and M and with L/M<1; said temporary storage means for said input data being associated respectively with said Q branches of said filter to provide said data to said multiplication means; said at least one coefficient memory being connected to said multiplication means to supply said coefficients to said multiplication means; and said multiplication means outputting filtered data y(m).
Claim 7
Dependent Claim
139 words
Digital filter architecture comprising: means for sharing input sampled data x(n); means for temporary storage of said input data x(n), e.g. a plurality Q of memories of shift register or FIFO type; Q branches of the filter; at least one other memory referred to as a "coefficient" memory for storing filter coefficients g m (p); means for multiplying data x(n) by the coefficients g m (p); means for performing interpolation by L; means for decimation by M, with integer L and M and with L/M<1; said temporary storage means for said input data being associated respectively with said Q branches of said filter to provide said data to said multiplication means; said at least one coefficient memory being connected to said multiplication means to supply said coefficients to said multiplication means; and said multiplication means outputting filtered data y(m).
Claim 8
Dependent Claim
16 words
Parallel digital filter architecture comprising a plurality of filters according to claim 5 connected in parallel.
Claim 9
Dependent Claim
13 words
Cascaded digital filter architecture comprising a plurality of filters according to claim 5.
Claim 10
Dependent Claim
19 words
A digital filter circuit according to the architecture of claim 5 for implementing a method according to claim 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-26 | 2004-03-27 | 2004-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-26 | 2008-03-27 | 2008-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-26 | 2012-03-27 | 2012-09-26 | $7700.00 | Window Closed / Lapsed |