Patent US6122718A successfully refreshed from Google Patents.
US6122718A
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Column address counter with minus two subtractor for address compare
Assignee: Longitude Semiconductor SARL
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Filing: 1997-12-11
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Granted: 2000-09-19
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Expires: 2017-12-11
Abstract
Abstract The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for producing a sequence of burst addresses, based on an external address. In addition, the counter drives the burst-done signal to indicate completion of the burst sequence. The counter includes a register for receiving the external address, an incrementor for advancing the external address to produce the next address of the sequence of burst addresses, a minus-two subtractor for determining a second-to-last burst address of the burst sequence, and a comparator. By utilizing the minus-two subtractor, the comparator can determine the end of the burst sequence earlier than conventional counters. This is because the minus-two subtractor determines the next-to-last address of the sequence, which allows the comparator to start asserting the burst-done signal at an earlier time.
Inventors
- 👤 Kazuya Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
92 words
A counter for producing a sequence of burst addresses from an external address and for producing a burst-done signal to indicate completion of the burst sequence, the counter comprising: a register for receiving the external address; a first circuit for advancing the external address to produce a next address of the sequence of burst addresses; a second circuit for determining a second-to-last burst address of the sequence of burst addresses; a third circuit for determining if the next address equals the second-to-last address and for asserting the burst-done signal in response thereto.
Claim 2
Dependent Claim
92 words
A counter for producing a sequence of burst addresses from an external address and for producing a burst-done signal to indicate completion of the burst sequence, the counter comprising: a register for receiving the external address; a first circuit for advancing the external address to produce a next address of the sequence of burst addresses; a second circuit for determining a second-to-last burst address of the sequence of burst addresses; a third circuit for determining if the next address equals the second-to-last address and for asserting the burst-done signal in response thereto.
Claim 3
Dependent Claim
13 words
The counter of claim 1 wherein the first circuit is an incrementor circuit.
Claim 4
Dependent Claim
14 words
The counter of claim 1 wherein the second circuit is a minus-two subtractor circuit.
Claim 5
Dependent Claim
12 words
The counter of claim 1 wherein the third circuit is a comparator.
Claim 6
Dependent Claim
22 words
The counter of claim 1 wherein the first circuit comprises a burst sequencer so that the sequence of burst addresses is programmable.
Claim 7
Dependent Claim
89 words
A synchronous memory device comprising a plurality of memory cell locations, a plurality of address pads for receiving an external address, and a counter for producing a plurality of internal addresses according to a predetermined sequence, the counter comprising: a first circuit for advancing the external address to produce a next address of the predetermined sequence; a second circuit for determining a second-to-last address of the sequence; a third circuit for determining if the next address equals the second-to-last address and for asserting a burst-done signal in response thereto.
Claim 8
Dependent Claim
89 words
A synchronous memory device comprising a plurality of memory cell locations, a plurality of address pads for receiving an external address, and a counter for producing a plurality of internal addresses according to a predetermined sequence, the counter comprising: a first circuit for advancing the external address to produce a next address of the predetermined sequence; a second circuit for determining a second-to-last address of the sequence; a third circuit for determining if the next address equals the second-to-last address and for asserting a burst-done signal in response thereto.
Claim 9
Dependent Claim
18 words
The synchronous memory device of claim 6 wherein the first circuit of the counter is an incrementor circuit.
Claim 10
Dependent Claim
19 words
The synchronous memory device of claim 6 wherein the second circuit of the counter is a minus-two subtractor circuit.
Claim 11
Dependent Claim
17 words
The synchronous memory device of claim 6 wherein the third circuit of the counter is a comparator.
Claim 12
Dependent Claim
27 words
The synchronous memory device of claim 6 wherein the first circuit of the counter comprises a burst sequencer so that the sequence of burst addresses is programmable.
Claim 13
Independent Claim
97 words
A method for providing a sequence of burst addresses based upon an external address, the method comprising the steps of: (a) receiving the external address into a register to become an intermediate address; (b) supplying the intermediate address in the register to a sequencing circuit; (c) sequencing the intermediate address that was supplied to the sequencing circuit to produce a next address of the sequence; (d) receiving the next address into the register to become the intermediate address; (e) comparing the intermediate address in the register with a reference address for determining when the sequence is complete.
Claim 14
Independent Claim
97 words
A method for providing a sequence of burst addresses based upon an external address, the method comprising the steps of: (a) receiving the external address into a register to become an intermediate address; (b) supplying the intermediate address in the register to a sequencing circuit; (c) sequencing the intermediate address that was supplied to the sequencing circuit to produce a next address of the sequence; (d) receiving the next address into the register to become the intermediate address; (e) comparing the intermediate address in the register with a reference address for determining when the sequence is complete.
Claim 15
Dependent Claim
34 words
The method of claim 11 further comprising the steps of: if the sequence is not complete, repeating the steps of (b), (c), (d), and (e); if the sequence is complete, asserting a burst-done signal.
Claim 16
Dependent Claim
19 words
The method of claim 11 further comprising the step of: (f) driving the intermediate address to a memory circuit.
Claim 17
Dependent Claim
15 words
The method of claim 11 wherein the reference address is determined from the external address.
Claim 18
Dependent Claim
18 words
The method of claim 11 wherein the reference address is determined by subtracting two from the external address.
Claim 19
Dependent Claim
18 words
The method of claim 11 wherein the reference address is determined by inverting part of the external address.
Claim 20
Dependent Claim
13 words
The method of claim 11 wherein the sequencing is done by an incrementor.
Claim 21
Dependent Claim
14 words
The method of claim 11 wherein the sequencing is programmable to different burst sequences.
Claim 22
Dependent Claim
191 words
A semiconductor memory comprising: a memory array including a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, a plurality of memory cells, and a plurality of sense amplifier circuits connected to the bit line pairs; a common data line pair for the plurality of the bit line pairs; a switch circuit selectively connecting a predetermined bit line pair of the plurality of the bit line pairs to the common data line pair; an adder circuit which outputs a sequence of addresses; an address holding circuit which holds an output address from the adder circuit as an input address of the adder circuit; a subtractor circuit which forms an output address before a last address of the sequence of addresses on the basis of a first address of the sequence of addresses; a comparator circuit which receives the input address of the adder circuit and the output address of the subtractor circuit; and a control circuit which controls the switch circuit based on the sequence of addresses; wherein the operation of the adder circuit is stopped by an agreement detection signal from the comparator circuit.
Claim 23
Dependent Claim
191 words
A semiconductor memory comprising: a memory array including a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, a plurality of memory cells, and a plurality of sense amplifier circuits connected to the bit line pairs; a common data line pair for the plurality of the bit line pairs; a switch circuit selectively connecting a predetermined bit line pair of the plurality of the bit line pairs to the common data line pair; an adder circuit which outputs a sequence of addresses; an address holding circuit which holds an output address from the adder circuit as an input address of the adder circuit; a subtractor circuit which forms an output address before a last address of the sequence of addresses on the basis of a first address of the sequence of addresses; a comparator circuit which receives the input address of the adder circuit and the output address of the subtractor circuit; and a control circuit which controls the switch circuit based on the sequence of addresses; wherein the operation of the adder circuit is stopped by an agreement detection signal from the comparator circuit.
Claim 24
Dependent Claim
21 words
A semiconductor memory according to claim 19, wherein the subtractor circuit is a circuit that subtracts two from the first address.
Claim 25
Dependent Claim
28 words
A semiconductor memory according to claim 20, wherein the first address is an external address and the initial value of the address holding circuit is the first address.
Claim 26
Dependent Claim
59 words
A semiconductor memory according to claim 21, further comprising: an internal clock generation circuit which generates an internal clock signal based on an external clock signal; wherein the adder circuit operates in synchronism with the internal clock signal. (e) comparing the address that was received into the register with a reference address for determining when the sequence is complete.
References Cited (Backward Citations)
US5208782A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-19 | 2004-03-20 | 2004-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-19 | 2008-03-20 | 2008-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-19 | 2012-03-20 | 2012-09-19 | $7700.00 | Window Closed / Lapsed |