Apparatus and method of providing stereo television audio signals

Claim 2

A circuit for providing stereo audio signals, comprising: an interface circuit coupled to receive an audio signal, said interface circuit providing a first audio input signal and a second audio input signal based on said audio signal; a processor coupled to said interface circuit, said processor executing instruction sequences to cause the processor to a) obtain a sum of said first audio input signal and said second audio input signal to provide a first value, b) obtain a difference of between said first audio input signal and said second audio input signal, and encoding said difference to provide an encoded difference value, c) multiply twice the encoded difference value with twice the first harmonic frequency of a synchronization signal to provide a second value, d) multiply a fundamental frequency of the synchronization signal with a predetermined number to provide a third value, and e) obtain a sum of said first, said second and said third values; whereby the instruction sequences cause the processor to generate a third audio input signal based on said first and said second audio input signals; and a first processing circuit coupled to said processor, said first processing circuit configured to generate a first audio output signal based on said third audio input signal.

Claim 3

The circuit of claim 1, wherein the predetermined number is 0.2.

Claim 4

The circuit of claim 1, wherein the synchronization signal is a video horizontal synchronization signal.

Claim 5

The circuit of claim 1, wherein the instruction sequences further cause the processor to filter said first and said second audio input signals prior to obtaining the sum.

Claim 6

The circuit of claim 1, wherein encoding includes DBX encoding.

Claim 7

The circuit of claim 1, wherein the interface circuit includes an analog-to-digital converter for digitizing said first and said second audio input signals.

Claim 8

The circuit of claim 1 further comprising: a second processing circuit coupled to said interface circuit, said second processing circuit configured to generate a second audio output signal based on said first audio input signal; and a third processing circuit coupled to said interface circuit, said third processing circuit configured to generate a third audio output signal based on said second audio input signal.

Claim 9

The circuit of claim 7, wherein said second processing circuit further comprises: an analog-to-digital converter coupled to said interface circuit for digitizing said first audio input signal; a modulator coupled to said analog-to-digital converter for modulating the digitized first audio input signal; a digital-to-analog converter coupled to said modulator for converting the digitized first audio input signal to an analog first audio input signal; and a filter coupled to said digital-to-analog converter for filtering said analog first audio input signal to provide said first audio output signal.

Claim 10

The circuit of claim 7, wherein said third processing circuit further comprises: an analog-to-digital converter coupled to said interface circuit for digitizing said second audio input signal; a modulator coupled to said analog-to-digital converter for modulating the digitized second audio input signal; a digital-to-analog converter coupled to said modulator for converting the digitized second audio input signal to an analog second audio input signal; and a filter coupled to said digital-to-analog converter for filtering said second analog audio input signal to provide said second audio output signal.

Claim 11

The circuit of claim 1, wherein said first processing circuit further comprises: a modulator coupled to said processor for modulating the digitized third audio input signal; a digital-to-analog converter coupled to said modulator for converting the digitized third audio input signal to an analog third audio input signal; and a filter coupled to said digital-to-analog converter for filtering said analog third audio input signal to provide said first audio output signal.

Claim 14

The method of claim 11, wherein the predetermined number is 0.2.

Claim 15

The method of claim 11, wherein the synchronization signal is a video horizontal synchronization signal.

Claim 16

The method of claim 11, wherein the stored instruction sequences further cause the processor to filter said first and said second audio input signals prior to obtaining the sum.

Claim 17

The method of claim 11, wherein encoding includes DBX encoding.

Claim 18

The method of claim 11, wherein the interface circuit includes an analog-to-digital converter for digitizing said first and said second audio input signals.

Claim 19

The method of claim 11, further comprising: modulating the digitized first audio input signal; converting the digitized first audio input signal to an analog first audio input signal; and filtering said analog first audio input signal to provide a second audio output signal.

Claim 20

The method of claim 11, further comprising: modulating the digitized second audio input signal; converting the digitized second audio input signal to an analog second audio input signal; and filtering said second analog audio input signal to provide a third audio output signal.

Claim 21

The method of claim 11, wherein generating a first audio output signal further comprises: modulating the digitized third audio input signal; converting the digitized third audio input signal to an analog third audio input signal; and filtering said analog third audio input signal to provide said first audio output signal.

Claim 22

A circuit for providing stereo audio signals, comprising: an interface circuit coupled to receive an audio signal, said interface circuit providing a first audio input signal and a second audio input signal based on said received audio signal; a first processing circuit coupled to said interface circuit, that is configured to generate a first and a second audio output signals based on said first and said second audio input signals; a processor coupled to said interface circuit, said processor executing instruction sequences, wherein the instruction sequences cause the processor to: a) obtain a sum of said first audio input signal and said second audio input signal to provide a first value; b) obtain a difference of between said first audio input signal and said second audio input signal, and encoding said difference to provide an encoded difference value; c) multiply twice the encoded difference value with twice the first harmonic frequency of a synchronization signal to provide a second value; d) multiply a fundamental frequency of the synchronization signal with a predetermined number to provide a third value; and e) obtain a sum of said first, said second and said third values; whereby the instruction sequences cause the processor to generate a third audio input signal based on said first and said second audio input signals; and a second processing circuit coupled to said processor, that is configured to generate a third audio output signal based on said third audio input signal.

Claim 23

A circuit for providing stereo audio signals, comprising: an interface circuit coupled to receive an audio signal, said interface circuit providing a first audio input signal and a second audio input signal based on said received audio signal; a first processing circuit coupled to said interface circuit, that is configured to generate a first and a second audio output signals based on said first and said second audio input signals; a processor coupled to said interface circuit, said processor executing instruction sequences, wherein the instruction sequences cause the processor to: a) obtain a sum of said first audio input signal and said second audio input signal to provide a first value; b) obtain a difference of between said first audio input signal and said second audio input signal, and encoding said difference to provide an encoded difference value; c) multiply twice the encoded difference value with twice the first harmonic frequency of a synchronization signal to provide a second value; d) multiply a fundamental frequency of the synchronization signal with a predetermined number to provide a third value; and e) obtain a sum of said first, said second and said third values; whereby the instruction sequences cause the processor to generate a third audio input signal based on said first and said second audio input signals; and a second processing circuit coupled to said processor, that is configured to generate a third audio output signal based on said third audio input signal.

Claim 24

The circuit of claim 20, wherein the predetermined number is 0.2.

Claim 25

The circuit of claim 20, wherein the synchronization signal is a video horizontal synchronization signal.

Claim 26

The circuit of claim 20, wherein the instruction sequences further cause the processor to filter said first and said second audio input signals prior to obtaining the sum.

Claim 27

The circuit of claim 20, wherein encoding includes DBX encoding.

Claim 28

The circuit of claim 20, wherein the interface circuit includes an analog-to-digital converter for digitizing said first and said second audio input signals.

Claim 29

The circuit of claim 25, wherein said first processing circuit further comprises: a modulator coupled to said interface circuit for modulating the digitized first audio input signal; a digital-to-analog converter coupled to said modulator for converting the digitized first audio input signal to an analog first audio input signal; and a filter coupled to said digital-to-analog converter for filtering said analog first audio input signal to provide said first audio output signal.

Claim 30

The circuit of claim 26, wherein said first processing circuit further comprises: a second modulator coupled to said interface circuit for modulating the digitized second audio input signal; a second digital-to-analog converter coupled to said modulator for converting the digitized second audio input signal to an analog second audio input signal; and second filter coupled to said digital-to-analog converter for filtering said second analog audio input signal to provide said second audio output signal.

Claim 31

The circuit of claim 25, wherein said second processing circuit comprises: a modulator coupled to said interface circuit for modulating the digitized third audio input signal; a digital-to-analog converter coupled to said modulator for converting the digitized third audio input signal to an analog third audio input signal; and a filter coupled to said digital-to-analog converter for filtering said analog third audio input signal to provide said third audio output signal.

Claim 32

A circuit for providing composite stereo audio signals based on a first and a second audio input signals, comprising: a processor, said processor executing stored instruction sequences, to cause the processor to a) obtain a sum of said first audio input signal and said second audio input signal to provide a first value, b) obtain a difference of between said first audio input signal and said second audio input signal, and encoding said difference to provide an encoded difference value, c) multiply twice the encoded difference value with twice the first harmonic frequency of a synchronization signal to provide a second value, d) multiply a fundamental frequency of the synchronization signal with a predetermined number to provide a third value, and e) obtain a sum of said first, said second and said third values; wherein the stored instruction sequences include process steps to cause the processor to generate a third audio input signal based on the first and the second audio input signals; and a processing circuit coupled to said processor, that is configured to generate a composite audio output signal based on said third audio input signal.

Claim 33

A circuit for providing composite stereo audio signals based on a first and a second audio input signals, comprising: a processor, said processor executing stored instruction sequences, to cause the processor to a) obtain a sum of said first audio input signal and said second audio input signal to provide a first value, b) obtain a difference of between said first audio input signal and said second audio input signal, and encoding said difference to provide an encoded difference value, c) multiply twice the encoded difference value with twice the first harmonic frequency of a synchronization signal to provide a second value, d) multiply a fundamental frequency of the synchronization signal with a predetermined number to provide a third value, and e) obtain a sum of said first, said second and said third values; wherein the stored instruction sequences include process steps to cause the processor to generate a third audio input signal based on the first and the second audio input signals; and a processing circuit coupled to said processor, that is configured to generate a composite audio output signal based on said third audio input signal.

Claim 34

The circuit of claim 29, wherein the synchronization signal is a video horizontal synchronization signal.

Claim 35

The circuit of claim 29, wherein encoding includes DBX encoding.