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US6121650A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device with increased charge retention capacity and method for forming the same

Assignee: Godo Kaisha IP Bridge 1
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Filing: 1997-10-29
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Granted: 2000-09-19
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Expires: 2017-10-29
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Abstract

Abstract A semiconductor device includes a gate electrode (4) formed of a conductive material on a semiconductor substrate (1) of one conductivity type with a gate insulating film (3) therebetween; first and second diffusion regions (5, 10) of another conductivity type formed on the semiconductor substrate (1) so as to sandwich the gate electrode (4); and a contact hole (17) for electrically connecting one (first) (10) of the first and second diffusion regions (5, 10) to a lower electrode (8) of a cell capacitor for storing charge therein, and has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of the first diffusion region (10) and the semiconductor substrate (1) (positive potential is applied to the n-type semiconductor side and zero or negative potential, to the p-type semiconductor side), a leakage current Ileak flows between the first diffusion region (10) and the semiconductor substrate (1), and the junction application voltage Vrev when the leakage current Ileak is Ileak=Cs×(Vbit/2)×(1/T)×(1/S) (where a charge storage capacitance in the cell capacitor is Cs, a voltage applied to a data line (12) connected to the other (second) (5) of the first and second diffusion regions (5, 10) is Vbit, a target charge retention time is T and an area of the first diffusion region (10) is S) is three times or higher than the voltage Vbit applied to the data line (12) at room temperature.

Inventors

  • 👤 Susumu Akamatsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 15:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10B12/02; H10B12/05; H10B12/50

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 164 words
A semiconductor device comprising: a gate electrode formed of a conductive material on a semiconductor substrate of one conductivity type with a gate insulating film therebetween; first and second diffusion regions of another conductivity type formed on said semiconductor substrate so as to sandwich said gate electrode; and a contact hole for electrically connecting one of said first and second diffusion regions to a lower electrode of a cell capacitor for storing charge therein, wherein said semiconductor device has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of said first diffusion region and said semiconductor substrate, a leakage current Ileak flows between said first diffusion region and said semiconductor substrate, and said junction application voltage Vrev when the leakage current Ileak is Ileak=Cs×(Vbit/2)×(1/T)×(1/S), is three times or higher than a voltage Vbit applied to a data line connected to the other of said first and second diffusion regions at room temperature.
Claim 2
Dependent Claim 164 words
A semiconductor device comprising: a gate electrode formed of a conductive material on a semiconductor substrate of one conductivity type with a gate insulating film therebetween; first and second diffusion regions of another conductivity type formed on said semiconductor substrate so as to sandwich said gate electrode; and a contact hole for electrically connecting one of said first and second diffusion regions to a lower electrode of a cell capacitor for storing charge therein, wherein said semiconductor device has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of said first diffusion region and said semiconductor substrate, a leakage current Ileak flows between said first diffusion region and said semiconductor substrate, and said junction application voltage Vrev when the leakage current Ileak is Ileak=Cs×(Vbit/2)×(1/T)×(1/S), is three times or higher than a voltage Vbit applied to a data line connected to the other of said first and second diffusion regions at room temperature.
Claim 3
Dependent Claim 47 words
A semiconductor device according to claim 1, wherein in dry etching in forming said contact hole, a damaged layer generated in said first diffusion region connected to said lower electrode of said capacitor is covered with a region having an impurity concentration of 1E18/cm 3 or higher.

References Cited (Backward Citations)

JPS622562A Cited
JPH02177359A Cited
US5440165A Cited
US5932906A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-09-19 2004-03-20 2004-09-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-09-19 2008-03-20 2008-09-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-09-19 2012-03-20 2012-09-19 $7700.00 Window Closed / Lapsed

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