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US6118692A
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Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
Assignee: BTG International Inc
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Filing: 1999-05-14
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Granted: 2000-09-12
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Expires: 2019-05-14
Abstract
Abstract Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.
Inventors
- 👤 Gerald J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5642; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 111
Claim 1
Independent Claim
247 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, and the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 2
Dependent Claim
247 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, and the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 3
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 1, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 4
Dependent Claim
243 words
The electrically alterable non-volatile multi-level memory according to claim 2, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 5
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 3, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 6
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 4, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 7
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 5, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 8
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 6, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 9
Dependent Claim
250 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 10
Dependent Claim
250 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 11
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 8, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 12
Dependent Claim
243 words
The electrically alterable non-volatile multi-level memory according to claim 9, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 13
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 10, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 14
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 11, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 15
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 12, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 16
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 13, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 17
Dependent Claim
273 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 18
Dependent Claim
273 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the second reading reference parameter is allocated substantially at a midpoint of the second state and the third state, the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 19
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 15, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 20
Dependent Claim
243 words
The electrically alterable non-volatile multi-level memory according to claim 16, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 21
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 17, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 22
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 18, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 23
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 19, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 24
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 20, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 25
Dependent Claim
264 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, and the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 26
Dependent Claim
264 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, and the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 27
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 22, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 28
Dependent Claim
270 words
The electrically alterable non-volatile multi-level memory according to claim 23, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 29
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 24, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 30
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 25, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 31
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 26, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 32
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 27, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 33
Dependent Claim
262 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state-and the fourth state.
Claim 34
Dependent Claim
262 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state-and the fourth state.
Claim 35
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 29, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 36
Dependent Claim
270 words
The electrically alterable non-volatile multi-level memory according to claim 30, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 37
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 31, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 38
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 32, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 39
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 33, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 40
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 34, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 41
Dependent Claim
288 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling a electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 42
Dependent Claim
288 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for controlling a electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the second reading reference electrical value is allocated substantially at a midpoint of the second state and the third state, the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 43
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 36, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 44
Dependent Claim
271 words
The electrically alterable non-volatile multi-level memory according to claim 37, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relation ship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 45
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 38, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 46
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 39, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 47
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 40, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 48
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 41, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 49
Dependent Claim
231 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and and wherein the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 50
Dependent Claim
231 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and and wherein the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 51
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 43, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 52
Dependent Claim
243 words
The electrically alterable non-volatile multi-level memory according to claim 44, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 53
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 45, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 54
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 46, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 55
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 47, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 56
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 48, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 57
Dependent Claim
230 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 58
Dependent Claim
230 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and wherein the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 59
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 50, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 60
Dependent Claim
243 words
The electrically alterable non-volatile multi-level memory according to claim 51, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 61
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 52, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 62
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 53, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 63
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 54, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 64
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 55, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 65
Dependent Claim
255 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and and wherein the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 66
Dependent Claim
255 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, and and wherein the first reading reference parameter is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference parameter is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 67
Dependent Claim
35 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 57, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 68
Dependent Claim
247 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 58, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for settling the parameter, of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
Claim 69
Dependent Claim
88 words
The electrically alterable non-volatile multi-level memory according to claim 59, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 70
Dependent Claim
41 words
The electrically alterable non-volatile multi-level memory according to claim 60, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 71
Dependent Claim
37 words
The electrically alterable non-volatile multi-level memory according to claim 61, wherein the operation for settling the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 72
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 62, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 73
Dependent Claim
243 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 74
Dependent Claim
243 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 75
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 64, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 76
Dependent Claim
270 words
The electrically alterable non-volatile multi-level memory according to claim 65, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 77
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 66, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 78
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 67, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 79
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 68, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 80
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 69, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 81
Dependent Claim
243 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 82
Dependent Claim
243 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 83
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 71, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 84
Dependent Claim
270 words
The electrically alterable non-volatile multi-level memory according to claim 72, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 85
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 73, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 86
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 74, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 87
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 75, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 88
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 76, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 89
Dependent Claim
268 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling a electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 90
Dependent Claim
268 words
An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells comprising: wherein an operation for controlling a electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation for reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value is carried out, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state, and the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 91
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 78, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 92
Dependent Claim
271 words
The electrically alterable non-volatile multi-level memory according to claim 79, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the operation additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relation ship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 93
Dependent Claim
90 words
The electrically alterable non-volatile multi-level memory according to claim 80, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 94
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 81, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 95
Dependent Claim
38 words
The electrically alterable non-volatile multi-level memory according to claim 82, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 96
Dependent Claim
33 words
The electrically alterable non-volatile multi-level memory according to claim 83, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 97
Dependent Claim
241 words
For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and thereafter reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 98
Dependent Claim
241 words
For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and thereafter reading status of the one non-volatile multi-level memory cell by interrogating a relationship between the electrical value and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, and wherein the third reading reference electrical value is allocated adjacent to the third state from a midpoint of the third state and the fourth state.
Claim 99
Dependent Claim
35 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 85, wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 100
Dependent Claim
39 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 86, wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 101
Dependent Claim
39 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 86, wherein the first reading reference electrical value is allocated adjacent to the second state from a midpoint of the first state and the second state.
Claim 102
Dependent Claim
274 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 87, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the method additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 103
Dependent Claim
94 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 89, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 104
Dependent Claim
46 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 90, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 105
Dependent Claim
42 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 91, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 106
Dependent Claim
37 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 92, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
Claim 107
Dependent Claim
274 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 88, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the method additionally comprises, after an operation for controlling the electrical value, of verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by interrogating a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state, wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
Claim 108
Dependent Claim
94 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 94, wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 109
Dependent Claim
46 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 94, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 110
Dependent Claim
42 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 96, wherein the operation for controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.
Claim 111
Dependent Claim
37 words
The method of operating the electrically alterable non-volatile multi-level memory according to claim 97, wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by a phenomenon of hot electron injection.
References Cited (Backward Citations)
US32401A
Cited
USRE32401E
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |