Patent US6118286A successfully refreshed from Google Patents.
US6118286A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device tester-to-handler Interface board with large test area
Assignee: Xilinx Inc
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Filing: 1997-08-18
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Granted: 2000-09-12
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Expires: 2017-08-18
Abstract
Abstract A semiconductor device tester and handler interface includes a tester and handler board. The board includes multiple test sites and has multiple layers of metallization traces. The handler side of the board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester side of the board has tester contacts located to interface with a tester. Vias connect metallization traces in one metallization layer to metallization traces in another layer. The traces and vias are arranged to form paths from a tester contact to a test socket. The test sites are placed close to and sometimes superimposed on the tester contacts receiving the test signals. Thus delay is minimized and with multiple test sites, throughput is increased.
Inventors
- 👤 Toby Alan Fredrickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2886; G01R31/2889; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; H; H05; H05K; H05K1/00; H05K1/02; H05K1/0266; H05K1/0268
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
132 words
A semiconductor device tester-to-handler interface printed circuit board comprising: at least three metallization layers each including a plurality of metallization traces; a plurality of vias, each via connecting two traces in two different metallization layers; a plurality of sockets attached to a top surface of said printed circuit board, each of said sockets for receiving a device to be tested; a plurality of tester contacts attached to a bottom surface of said printed circuit board; said metallization traces and vias being arranged to form a plurality of electrical paths, each path connecting one of said tester contacts to one of said sockets; whereby it is possible to locate the sockets in a large area above the tester contacts without electrical contact between a socket and a tester contact located below the socket.
Claim 2
Dependent Claim
132 words
A semiconductor device tester-to-handler interface printed circuit board comprising: at least three metallization layers each including a plurality of metallization traces; a plurality of vias, each via connecting two traces in two different metallization layers; a plurality of sockets attached to a top surface of said printed circuit board, each of said sockets for receiving a device to be tested; a plurality of tester contacts attached to a bottom surface of said printed circuit board; said metallization traces and vias being arranged to form a plurality of electrical paths, each path connecting one of said tester contacts to one of said sockets; whereby it is possible to locate the sockets in a large area above the tester contacts without electrical contact between a socket and a tester contact located below the socket.
Claim 3
Dependent Claim
38 words
A semiconductor device tester-to-handler interface printed circuit board as in claim 1 wherein at least some of said sockets attached to a top surface of said printed circuit board are located directly above some of said tester contacts.
Claim 4
Dependent Claim
40 words
A semiconductor device tester-to-handler interface printed circuit board as in claim 1 wherein at least some of said vias are formed by drilling via holes before joining said metallization layers and electroplating said via holes after joining said metallization layers.
Claim 5
Dependent Claim
39 words
A semiconductor device tester-to-handler interface printed circuit board as in claim 3 wherein when two of said metallization traces are to be connected by a via, metallization traces are not formed in the same locations in other metallization layers.
Claim 6
Dependent Claim
27 words
A semiconductor device tester-to-handler interface printed circuit board as in claim 3 wherein said vias for connecting two metallization layers extend through all of said metallization layers.
Claim 7
Dependent Claim
48 words
A semiconductor device tester-to-handler interface printed circuit board as in claim 1 wherein those of said vias in metallization layers interior to said printed circuit board are formed and electroplated before metallization layers at a surface of said printed circuit board are attached to said printed circuit board.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |