§
Luxuse
Patent Intelligence
Sign In
Patent US6110767A successfully refreshed from Google Patents.
← Back to Patent Explorer
US6110767A Expired / Lapsed US ⏱️ 0.0 years remaining

Reversed MOS

Assignee: Vanguard International Semiconductor Corp
•
Filing: 1998-07-16
•
Granted: 2000-08-29
•
Expires: 2018-07-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A new method for fabricating a reversed MOS structure in order to provide latchup immunity in the manufacture of integrated circuits is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. A dielectric layer is formed on the surface of the semiconductor substrate in the active area. A polysilicon layer is deposited overlying the dielectric layer and patterned. A mask is formed over a portion of the polysilicon layer in the active area. Ions are implanted into the polysilicon layer not covered by the mask to form implanted regions within the polysilicon layer and simultaneously form implanted regions within the substrate adjacent to the polysilicon layer wherein the implanted regions in the polysilicon layer form source and drain regions and wherein the polysilicon layer covered by the mask forms a channel region and wherein the implanted regions within the substrate diffuse together to form a gate electrode underlying the channel region.

Inventors

  • 👤 Shu-Fang Wu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/0172; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/83138; H10D84/85; H10D84/856; H10D84/8311; H10D84/8312

Claims Analysis

Total Claims: 27
Claim 1
Independent Claim 146 words
A method of fabricating an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions and wherein said polysilicon layer covered by said mask forms a channel region and wherein said implanted regions within said substrate diffuse together to form a gate electrode underlying said channel region.
Claim 2
Independent Claim 146 words
A method of fabricating an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions and wherein said polysilicon layer covered by said mask forms a channel region and wherein said implanted regions within said substrate diffuse together to form a gate electrode underlying said channel region.
Claim 3
Dependent Claim 24 words
The method according to claim 1 wherein said dielectric layer comprises silicon oxide and has a thickness of between about 60 and 150 Angstroms.
Claim 4
Dependent Claim 20 words
The method according to claim 1 wherein said polysilicon layer has a thickness of between about 2000 and 4000 Angstroms.
Claim 5
Dependent Claim 42 words
The method according to claim 1 wherein said step of implanting said ions comprises implanting Arsenic ions at an energy of 30 to 50 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 6
Dependent Claim 42 words
The method according to claim 1 wherein said step of implanting said ions comprises implanting Phosphorus ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 7
Dependent Claim 42 words
The method according to claim 1 wherein said step of implanting said ions comprises implanting boron ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 8
Dependent Claim 43 words
The method according to claim 1 wherein said step of implanting said ions comprises implanting BF 2 ions at an energy of 30 to 70 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 9
Dependent Claim 28 words
The method according to claim 1 wherein said channel region between said implanted regions within said semiconductor substrate has a width of between about 1 and 20 microns.
Claim 10
Dependent Claim 27 words
The method according to claim 1 wherein said channel region between said implanted regions within said semiconductor substrate has a width of less than about 3 microns.
Claim 11
Independent Claim 169 words
A method of fabricating a reversed MOS device in the fabrication of an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions of said reversed MOS device and wherein said polysilicon layer covered by said mask forms a channel region of said reversed MOS device and wherein said implanted regions within said substrate diffuse together to form a gate electrode of said reversed MOS device underlying said channel region.
Claim 12
Independent Claim 169 words
A method of fabricating a reversed MOS device in the fabrication of an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions of said reversed MOS device and wherein said polysilicon layer covered by said mask forms a channel region of said reversed MOS device and wherein said implanted regions within said substrate diffuse together to form a gate electrode of said reversed MOS device underlying said channel region.
Claim 13
Dependent Claim 24 words
The method according to claim 10 wherein said dielectric layer comprises silicon oxide and has a thickness of between about 60 and 150 Angstroms.
Claim 14
Dependent Claim 20 words
The method according to claim 10 wherein said polysilicon layer has a thickness of between about 2000 and 4000 Angstroms.
Claim 15
Dependent Claim 42 words
The method according to claim 10 wherein said step of implanting said ions comprises implanting Arsenic ions at an energy of 30 to 50 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 16
Dependent Claim 42 words
The method according to claim 10 wherein said step of implanting said ions comprises implanting Phosphorus ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 17
Dependent Claim 42 words
The method according to claim 10 wherein said step of implanting said ions comprises implanting boron ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 18
Dependent Claim 43 words
The method according to claim 10 wherein said step of implanting said ions comprises implanting BF 2 ions at an energy of 30 to 70 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 19
Dependent Claim 28 words
The method according to claim 10 wherein said channel region between said implanted regions within said semiconductor substrate has a width of between about 1 and 20 microns.
Claim 20
Dependent Claim 27 words
The method according to claim 10 wherein said channel region between said implanted regions within said semiconductor substrate has a width of less than about 3 microns.
Claim 21
Independent Claim 190 words
A method of fabricating a reversed MOS device in the fabrication of an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions of said reversed MOS device and wherein said polysilicon layer covered by said mask forms a channel region of said reversed MOS device and wherein the width of said channel region between said implanted regions within said substrate is between about 1 and 20 microns whereby said implanted regions within said substrate diffuse together to form a gate electrode of said reversed MOS device underlying said channel region.
Claim 22
Independent Claim 190 words
A method of fabricating a reversed MOS device in the fabrication of an integrated circuit device comprising: providing an active area in a semiconductor substrate separated from other active areas by isolation regions; forming a dielectric layer on the surface of said semiconductor substrate in said active area; depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer; forming a mask over a portion of said polysilicon layer in said active area; and implanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions of said reversed MOS device and wherein said polysilicon layer covered by said mask forms a channel region of said reversed MOS device and wherein the width of said channel region between said implanted regions within said substrate is between about 1 and 20 microns whereby said implanted regions within said substrate diffuse together to form a gate electrode of said reversed MOS device underlying said channel region.
Claim 23
Dependent Claim 42 words
The method according to claim 19 wherein said step of implanting said ions comprises implanting Arsenic ions at an energy of 30 to 50 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 24
Dependent Claim 42 words
The method according to claim 19 wherein said step of implanting said ions comprises implanting Phosphorus ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form N+ implanted regions.
Claim 25
Dependent Claim 42 words
The method according to claim 19 wherein said step of implanting said ions comprises implanting boron ions at an energy of 20 to 30 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 26
Dependent Claim 43 words
The method according to claim 19 wherein said step of implanting said ions comprises implanting BF 2 ions at an energy of 30 to 70 KeV and dosage of 1 E 13 to 3 E 15 atoms/cm 2 to form P+ implanted regions.
Claim 27
Dependent Claim 27 words
The method according to claim 19 wherein said channel region between said implanted regions within said semiconductor substrate has a width of less than about 3 microns.

References Cited (Backward Citations)

US4430792A Cited
US4685196A Cited
US5296727A Cited
US5441900A Cited
US5807769A Cited
US5451534A Cited
US5736435A Cited
US5661051A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-08-29 2004-02-28 2004-08-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-08-29 2008-02-28 2008-08-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-08-29 2012-02-28 2012-08-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag