Multi-master PCI bus system within a single integrated circuit

Claim 2

A multiple bus master PCI (peripheral component interconnect) bus system within an integrated circuit, comprising: an integrated circuit fabricated onto a semiconductor die; an internal PCI bus built into said integrated circuit, said internal PCI bus adapted to transmit data signals thereon; a plurality of PCI agents built into said integrated circuit, each of said plurality of PCI agents for performing a function, each of said plurality of PCI agents coupled to said internal PCI bus, said internal PCI bus and said plurality of PCI agents built into said integrated circuit on said semiconductor die to form a high performance device, wherein at least one of said plurality of PCI agents is a pre-existing PCI agent with respect to said high performance device; and a parity generator circuit built into said integrated circuit, said parity generator circuit adapted to respond to parity generation and checking signals from at least one of said plurality of PCI agents.

Claim 3

The multiple bus master PCI system of claim 1, further comprising: an arbiter circuit built into said integrated circuit, said arbiter circuit adapted to arbitrate among said plurality of PCI agents for ownership of said internal PCI bus.

Claim 4

The multiple bus master PCI system of claim 1, further comprising: a PCI to PCI bridge built into said integrated circuit, said PCI to PCI bridge adapted to interface said internal PCI bus with an external PCI bus such that said plurality of PCI agents can communicate with said external PCI bus.

Claim 5

The multiple bus master PCI system of claim 1, wherein said internal PCI bus is adapted to substantially comply with a PCI bus specification with respect to interfacing with said plurality of PCI agents.

Claim 6

The multiple bus master PCI system of claim 3, wherein said PCI to PCI bridge is adapted to synchronize signals on said internal PCI bus with said external PCI bus, wherein said internal PCI bus and said external PCI bus operate at different frequencies.

Claim 7

The multiple bus master PCI system of claim 3, wherein said PCI to PCI bridge is a buffer based bridge adapted to interface said internal PCI bus with said external PCI bus, wherein said internal PCI bus and said external PCI bus operate at the same frequency.

Claim 8

A fully integrated, single semiconductor die PCI (peripheral component interconnect) bus system, comprising: an integrated circuit fabricated onto a semiconductor die; an internal PCI bus built into said integrated circuit, said internal PCI bus adapted to transmit data signals thereon; a plurality of PCI agents built into said integrated circuit, each of said plurality of PCI agents for performing a function, each of said plurality of PCI agents coupled to said internal PCI bus, said internal PCI bus and said plurality of PCI agents built into said integrated circuit on said semiconductor die to form a high performance device, wherein at least one of said plurality of PCI agents is a pre-existing PCI agent with respect to said high performance device; an arbiter circuit built into said integrated circuit, said arbiter circuit adapted to arbitrate among said plurality of PCI agents for ownership of said internal PCI bus; a parity generator circuit built into said integrated circuit, said parity generator circuit adapted to respond to parity generation and checking from at least one of said plurality of PCI agents; and a PCI to PCI bridge built into said integrated circuit, said PCI to PCI bridge adapted to interface said internal PCI bus with an external PCI bus such that said plurality of PCI agents can communicate with said external PCI bus.

Claim 9

A fully integrated, single semiconductor die PCI (peripheral component interconnect) bus system, comprising: an integrated circuit fabricated onto a semiconductor die; an internal PCI bus built into said integrated circuit, said internal PCI bus adapted to transmit data signals thereon; a plurality of PCI agents built into said integrated circuit, each of said plurality of PCI agents for performing a function, each of said plurality of PCI agents coupled to said internal PCI bus, said internal PCI bus and said plurality of PCI agents built into said integrated circuit on said semiconductor die to form a high performance device, wherein at least one of said plurality of PCI agents is a pre-existing PCI agent with respect to said high performance device; an arbiter circuit built into said integrated circuit, said arbiter circuit adapted to arbitrate among said plurality of PCI agents for ownership of said internal PCI bus; a parity generator circuit built into said integrated circuit, said parity generator circuit adapted to respond to parity generation and checking from at least one of said plurality of PCI agents; and a PCI to PCI bridge built into said integrated circuit, said PCI to PCI bridge adapted to interface said internal PCI bus with an external PCI bus such that said plurality of PCI agents can communicate with said external PCI bus.

Claim 10

The single die PCI bus system of claim 7, wherein said PCI to PCI bridge is adapted to synchronize signals on said internal PCI bus with said external PCI bus wherein said internal PCI bus and said external PCI bus operate at different frequencies.

Claim 11

The single die PCI bus system of claim 7, wherein said PCI to PCI bridge is buffer based bridge adapted to interface said internal PCI bus and said external PCI bus wherein said internal PCI bus and said external PCI bus operate at the same frequency.

Claim 12

The single die PCI bus system of claim 7, wherein said internal PCI bus is adapted to substantially comply with a PCI bus specification with respect to interfacing with said plurality of PCI agents.

Claim 15

The method of claim 11, wherein step b) further comprises the step of coupling at least one pre-existing design of at least one pre-existing PCI agent to said design of said internal PCI bus such that a large percentage of each of said at least one pre-existing design is reused in a substantially unchanged condition.