Patent US6108723A successfully refreshed from Google Patents.
US6108723A
Expired / Lapsed
US
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System for implementing hardware automated control of burst mode data transfer over a communication link between devices operating in a block mode
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1998-07-20
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Granted: 2000-08-22
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Expires: 2018-07-20
Abstract
Abstract Burst-mode data transfers between a SCSI host bus adapter and at least one SCSI bus device interface adapter are implemented by hardware. For a first embodiment of the invention, the device interface adapter is equipped with a first, second and third data registers, a comparator, a subtractor, and control logic in the form of an application specific integrated circuit. When a burst-mode transfer is requested, the first register is programmed with a value corresponding to the length of the transfer in bytes, and the second register is programmed with the maximum possible number of bytes in a burst. The comparator then compares the value in stored in the first register with the value stored in the second register and determines which is the smaller. The smaller of the two values is written to the third register. The subtractor then subtracts said third value from said first value to obtain a remainder value. The first value is then replaced with a new first value equal to said remainder value. The control logic orchestrates the steps of comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and causing the steps of comparing, storing, subtracting and replacing to be repeated until said third value is equal to zero. Initial loading of the first and second registers is performed by either the control logic or by a microprocessor. For an alternate embodiment of the invention, the control logic, the comparator and the subtractor are replaced by a microprocessor.
Inventors
- 👤 Mark J. Simms
- 👤 R. Alexis Takasugi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:11
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
213 words
A method for implementing automated control of burst-mode transfers of a data record between a transmitting controller and a receiving controller over a communication link, the method comprising the steps of: (a) providing first, second and third data registers; (b) storing a value in the first data register corresponding to the total length of the transfer in data units; (c) storing a value in the second data register corresponding to the maximum possible number of data units in a burst; (d) comparing the value stored in the first data register with the value stored in the second data register, thereby determining which of the two values is the smaller value; (e) storing said smaller value, which is the actual burst length, to the third register; (f) subtracting the value stored in the third register from the value stored in the first data register to provide a remainder value which represents the total number of data units remaining in the transfer; (g) replacing the value stored in the first register with the remainder value; (h) transferring the amount of data represented by the value stored in the third register from the transmitting controller to the receiving controller; and (i) repeating steps (d) through (h) until the value in the first data register is zero.
Claim 2
Independent Claim
213 words
A method for implementing automated control of burst-mode transfers of a data record between a transmitting controller and a receiving controller over a communication link, the method comprising the steps of: (a) providing first, second and third data registers; (b) storing a value in the first data register corresponding to the total length of the transfer in data units; (c) storing a value in the second data register corresponding to the maximum possible number of data units in a burst; (d) comparing the value stored in the first data register with the value stored in the second data register, thereby determining which of the two values is the smaller value; (e) storing said smaller value, which is the actual burst length, to the third register; (f) subtracting the value stored in the third register from the value stored in the first data register to provide a remainder value which represents the total number of data units remaining in the transfer; (g) replacing the value stored in the first register with the remainder value; (h) transferring the amount of data represented by the value stored in the third register from the transmitting controller to the receiving controller; and (i) repeating steps (d) through (h) until the value in the first data register is zero.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein said first and second registers are programmed when a transfer request is received.
Claim 4
Dependent Claim
12 words
The method of claim 1, wherein said data units are 8-bit bytes.
Claim 5
Dependent Claim
25 words
The method of claim 1, which further comprises the step of providing control logic which manages the steps of storing, comparing, subtracting, replacing, and transferring.
Claim 6
Dependent Claim
17 words
The method of claim 4, wherein said control logic is incorporated in an application specific integrated circuit.
Claim 7
Dependent Claim
29 words
The method of claim 4, which further comprises the step of providing a comparator for performing the step of comparing, and a subtractor for performing the step of subtracting.
Claim 8
Dependent Claim
41 words
The method of claim 1, which further comprises the step of providing a microprocessor and a local data bus interconnecting the microprocessor with the first, second and third data registers for performing the steps of storing, comparing, subtracting, replacing, and transferring.
Claim 9
Dependent Claim
38 words
The method of claim 7, which further comprises the step of providing a read-only memory in which is stored program code readable by said microprocessor; said program code managing the steps of storing, comparing, subtracting, replacing, and transferring.
Claim 10
Dependent Claim
21 words
The method of claim 1, wherein burst-mode transfers are between a between the host bus adapter and a device interface adapter.
Claim 11
Dependent Claim
13 words
The method of claim 9, wherein said communication bus is a SCSI bus.
Claim 12
Dependent Claim
26 words
The method of claim 9, wherein said data registers, said microprocessor, said local data bus, and said read-only memory are on board the device interface adapter.
Claim 13
Dependent Claim
43 words
The method of claim 9, wherein each device interface adapter on the bus has its own microprocessor, first, second and third data registers, read-only memory and local data bus for controlling burst-mode transfers between that device interface adapter and the host bus adapter.
Claim 14
Dependent Claim
229 words
In combination with a SCSI bus coupled to a host system bus via a host bus adapter, a device interface adapter which couples the SCSI bus to at least one peripheral device, and which implements hardware-automated control of burst-mode transfers over the SCSI bus, said device interface adapter comprising: (a) a first data register for storing a first value which represents the total number of data units remaining in a each burst-mode data transfer; (b) a second data register for storing a second value which represents the maximum size of a burst in data units; (c) a third data register for storing a third value which represents the actual size of the next burst to be transferred; (d) a read-only memory for storing program code for managing burst-mode transfers; (e) a microprocessor for performing the steps of storing said first and second values at the start of a burst-mode transfer, comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and repeating the steps of comparing, storing, subtracting and replacing until said third value is equal to zero, said microprocessor coupled to said SCSI bus and to said first, second and third registers.
Claim 15
Dependent Claim
229 words
In combination with a SCSI bus coupled to a host system bus via a host bus adapter, a device interface adapter which couples the SCSI bus to at least one peripheral device, and which implements hardware-automated control of burst-mode transfers over the SCSI bus, said device interface adapter comprising: (a) a first data register for storing a first value which represents the total number of data units remaining in a each burst-mode data transfer; (b) a second data register for storing a second value which represents the maximum size of a burst in data units; (c) a third data register for storing a third value which represents the actual size of the next burst to be transferred; (d) a read-only memory for storing program code for managing burst-mode transfers; (e) a microprocessor for performing the steps of storing said first and second values at the start of a burst-mode transfer, comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and repeating the steps of comparing, storing, subtracting and replacing until said third value is equal to zero, said microprocessor coupled to said SCSI bus and to said first, second and third registers.
Claim 16
Dependent Claim
14 words
The host interface adapter of claim 13, wherein said data units are 8-bit bytes.
Claim 17
Dependent Claim
25 words
The host interface adapter of claim 13, wherein said microprocessor is coupled to said first, second and third data registers via a local data bus.
Claim 18
Dependent Claim
252 words
In combination with a SCSI bus coupled to a host system bus via a host bus adapter, a device interface adapter which couples the SCSI bus to at least one peripheral device, and which implements hardware-automated control of burst-mode transfers over the SCSI bus, said device interface adapter comprising: (a) a first data register for storing a first value which represents the total number of data units remaining in a each burst-mode data transfer; (b) a second data register for storing a second value which represents the maximum size of a burst in data units; (c) a third data register; (d) a comparator for comparing said first and second values and writing a third value, which is the smaller of said first and second values, to said third register; (e) a subtractor for subtracting said third value from said first value to obtain a remainder value, and replacing said first value with a new first value equal to said remainder value; (f) control logic for orchestrating the steps of comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and causing the steps of comparing, storing, subtracting and replacing to be repeated until said first value is equal to zero, said control logic coupled to said SCSI bus and to said first, second and third registers.
Claim 19
Dependent Claim
252 words
In combination with a SCSI bus coupled to a host system bus via a host bus adapter, a device interface adapter which couples the SCSI bus to at least one peripheral device, and which implements hardware-automated control of burst-mode transfers over the SCSI bus, said device interface adapter comprising: (a) a first data register for storing a first value which represents the total number of data units remaining in a each burst-mode data transfer; (b) a second data register for storing a second value which represents the maximum size of a burst in data units; (c) a third data register; (d) a comparator for comparing said first and second values and writing a third value, which is the smaller of said first and second values, to said third register; (e) a subtractor for subtracting said third value from said first value to obtain a remainder value, and replacing said first value with a new first value equal to said remainder value; (f) control logic for orchestrating the steps of comparing said first and second values, storing the smaller of said first and second values in said third register, subtracting said third value from said first value to give a remainder value, replacing said first value with a new first value equal to said remainder value, and causing the steps of comparing, storing, subtracting and replacing to be repeated until said first value is equal to zero, said control logic coupled to said SCSI bus and to said first, second and third registers.
Claim 20
Dependent Claim
23 words
The device interface adapter of claim 16, wherein said control logic stores said first and second values in said first and second registers.
Claim 21
Dependent Claim
45 words
The device interface adapter of claim 16, which further comprises: a microprocessor for loading an initial set of said first and second values in said first and second registers, respectively; and a local data bus which couples said microprocessor to said first and second registers.
Claim 22
Dependent Claim
14 words
The device interface adapter of claim 16, wherein said data units are eight-bit bytes.
Claim 23
Dependent Claim
19 words
The device interface adapter of claim 16, wherein said control logic is incorporated in an application specific integrated circuit.
References Cited (Backward Citations)
US4722069A
Cited
US5179663A
Cited
US4989173A
Cited
US5185694A
Cited
US5128891A
Cited
US5550987A
Cited
US5717949A
Cited
US5691719A
Cited
US5710800A
Cited
US5809260A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-22 | 2004-02-21 | 2004-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-22 | 2008-02-21 | 2008-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-22 | 2012-02-21 | 2012-08-22 | $7700.00 | Window Closed / Lapsed |