Method and apparatus for the generation of frequency hopping sequences

Claim 2

A frequency hopping generator for use in a wireless communication network, comprising: at least one permutation (PERM) processing module for processing a first portion of a clock signal as a function of at least one PERM address signal, wherein the PERM module performs a permutation of the first portion of the clock signal; and at least one exclusive OR (XOR) processing module, arranged in series with said at least one PERM module, for processing a second portion of said clock signal as a function of at least one XOR address signal; wherein an output of said serially arranged at least one PERM and XOR modules defines one of a plurality of hop numbers; wherein changes in said address signals produce a substantially instantaneous change in an output sequence of said hop numbers; and wherein changes in either of said first and second portions of said clock signal produce a substantially instantaneous change in a phase of an output sequence of said hop numbers.

Claim 3

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output, wherein the PERM1 processing module performs a permutation of the first portion of the clock signal; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers.

Claim 4

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output, wherein the PERM1 processing module performs a permutation of the first portion of the clock signal; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers.

Claim 5

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, wherein said first PERM1 processing module selectively switches bit positions in said first portion of said clock signal on the basis of said PERM1 selection address.

Claim 6

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, wherein said first PERM1 processing module selectively switches bit positions in said first portion of said clock signal on the basis of said PERM1 selection address.

Claim 7

The frequency hopping generator of claim 2, wherein said first XOR1 processing module performs a bit-wise exclusive OR logic function on the PERM1 output on the basis of said XOR1 selection address.

Claim 8

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a second XOR (XOR2) processing module having a first XOR2 input for receiving a second portion of said clock signal and a second XOR2 input for receiving an XOR2 selection address, and having an output defining said PERM1 selection address; and a third XOR (XOR3) processing module having a first XOR3 input for receiving a third portion of said clock signal and a second XOR3 input for receiving an XOR3 selection address, and having an output defining said XOR2 selection address.

Claim 9

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a second XOR (XOR2) processing module having a first XOR2 input for receiving a second portion of said clock signal and a second XOR2 input for receiving an XOR2 selection address, and having an output defining said PERM1 selection address; and a third XOR (XOR3) processing module having a first XOR3 input for receiving a third portion of said clock signal and a second XOR3 input for receiving an XOR3 selection address, and having an output defining said XOR2 selection address.

Claim 10

The frequency hopping generator of claim 5, further comprising: a second PERM (PERM2) processing module having a first PERM2 input for receiving a fourth portion of said clock signal and a second PERM2 input for receiving a PERM2 selection address, and having a first PERM2 output defining said first XOR2 input of said second XOR2 processing module and having a second PERM2 output defining said first XOR3 input of said third XOR3 processing module.

Claim 11

The frequency hopping generator of claim 5, wherein said first portion of said clock signal comprises least significant bits of said clock signal and said second and third portions of said clock signal comprise higher order bits of said clock signal.

Claim 12

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a modulo M adder having a first adder input for receiving said XOR1 output defining said one of said Z hop numbers, and having a second input for receiving a second portion of said clock signal, and having an adder output for outputing one of M hop numbers.

Claim 13

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a modulo M adder having a first adder input for receiving said XOR1 output defining said one of said Z hop numbers, and having a second input for receiving a second portion of said clock signal, and having an adder output for outputing one of M hop numbers.

Claim 14

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a memory for storing a plurality of hop frequencies corresponding to said Z output hop numbers, wherein one of said hop frequencies is selected on the basis of an input hop number generated by said first XOR1 module.

Claim 15

A frequency hopping generator for use in a wireless communication network, comprising: a first permutation (PERM1) processing module having a first PERM1 input for receiving a first portion of a clock signal and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output; and a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving said PERM1 output and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output defining one of a plurality of Z hop numbers, and further comprising: a memory for storing a plurality of hop frequencies corresponding to said Z output hop numbers, wherein one of said hop frequencies is selected on the basis of an input hop number generated by said first XOR1 module.

Claim 16

The frequency hopping generator of claim 9, wherein said frequencies are arranged such that consecutive hop numbers in a hop sequence are mapped into non-consecutive hop frequencies in said memory.

Claim 17

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, wherein the PERM1 processing module performs a permutation of the XOR1 output.

Claim 18

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, wherein the PERM1 processing module performs a permutation of the XOR1 output.

Claim 19

The frequency hopping generator of claim 11, wherein said first XOR1 processing module performs a bit-wise exclusive OR logic function on the first portion of the clock signal on the basis of said XOR1 selection address.

Claim 20

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, wherein said first PERM1 processing module selectively switches bit positions in said XOR1 output on the basis of said PERM1 selection address.

Claim 21

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, wherein said first PERM1 processing module selectively switches bit positions in said XOR1 output on the basis of said PERM1 selection address.

Claim 22

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, further comprising: a second XOR (XOR2) processing module having a first XOR2 input for receiving a second portion of said clock signal and a second XOR2 input for receiving an XOR2 selection address, and having an output defining said XOR1 selection address; and a third XOR (XOR3) processing module having a first XOR3 input for receiving a third portion of said clock signal and a second XOR3 input for receiving an XOR3 selection address, and having an output defining said PERM1 selection address.

Claim 23

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, further comprising: a second XOR (XOR2) processing module having a first XOR2 input for receiving a second portion of said clock signal and a second XOR2 input for receiving an XOR2 selection address, and having an output defining said XOR1 selection address; and a third XOR (XOR3) processing module having a first XOR3 input for receiving a third portion of said clock signal and a second XOR3 input for receiving an XOR3 selection address, and having an output defining said PERM1 selection address.

Claim 24

The frequency hopping generator of claim 14, further comprising: a second PERM (PERM2) processing module having a first PERM2 input for receiving a fourth portion of said clock signal and a second PERM2 input for receiving a PERM2 selection address, and having a first PERM2 output defining said first XOR2 input of said second XOR2 processing module and having a second PERM2 output defining said first XOR3 input of said third XOR3 processing module.

Claim 25

The frequency hopping generator of claim 14, wherein said first portion of said clock signal comprises least significant bits of said clock signal and said second and third portions of said clock signal comprise higher order bits of said clock signal.

Claim 26

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, and further comprising: a modulo M adder having a first adder input for receiving said XOR1 output defining said one of said Z hop numbers, and having a second input for receiving a second portion of said clock signal, and having an adder output for outputing one of M hop numbers.

Claim 27

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, and further comprising: a modulo M adder having a first adder input for receiving said XOR1 output defining said one of said Z hop numbers, and having a second input for receiving a second portion of said clock signal, and having an adder output for outputing one of M hop numbers.

Claim 28

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, and further comprising: a memory for storing a plurality of hop frequencies corresponding to said Z output hop numbers, wherein one of said hop frequencies is selected on the basis of an input hop number generated by said first PERM1 module.

Claim 29

A frequency hopping generator for use in a wireless communication network, comprising: a first exclusive OR (XOR1) processing module having a first XOR1 input for receiving a first portion of a clock signal and having a second XOR1 input for receiving an XOR1 selection address, and having an XOR1 output; and a first permutation (PERM1) processing module having a first PERM1 input for receiving said XOR1 output and a second PERM1 input for receiving a PERM1 selection address, and having a PERM1 output defining one of a plurality of Z hop numbers, and further comprising: a memory for storing a plurality of hop frequencies corresponding to said Z output hop numbers, wherein one of said hop frequencies is selected on the basis of an input hop number generated by said first PERM1 module.

Claim 30

The frequency hopping generator of claim 18, wherein said frequencies are arranged such that consecutive hop numbers in a hop sequence are mapped into non-consecutive hop frequencies in said memory.

Claim 33

The method of claim 20, wherein said permutation processing precedes said exclusive OR processing.

Claim 34

The method of claim 20, wherein said exclusive OR processing precedes said permutation processing.

Claim 35

The method of claim 20, further including the steps of: performing exclusive OR processing on a third portion of said clock signal and a second permutation address to generate said first permutation address; and performing exclusive OR processing on a fourth portion of said clock signal and a second exclusive OR address to generate said first exclusive OR address.

Claim 36

The method of claim 23, further including the step of: performing permutation processing on a fifth portion of said clock signal to generate said second and third portions of said clock signal.

Claim 37

The method of claim 20, further including the step of: processing said one of Z frequency hop numbers using a modulo M adder to generate one of M frequency hop numbers.

Claim 38

The method of claim 20, further including the step of: accessing a memory on the basis of said one of said Z output frequency hop numbers to retrieve one of a plurality of output hop frequencies, wherein said memory is so organized such that consecutive hop numbers correspond to non-consecutive hop frequencies.

Claim 39

A frequency hopping generator for use in a wireless communication network, comprising: a permutation processing module having a first input for receiving a first portion of a clock signal and a second input for receiving a selection address, and having an output defining one of a plurality of hop numbers, wherein the permutation processing module performs a permutation of the first portion of the clock signal.

Claim 40

A frequency hopping generator for use in a wireless communication network, comprising: a permutation processing module having a first input for receiving a first portion of a clock signal and a second input for receiving a selection address, and having an output defining one of a plurality of hop numbers, wherein the permutation processing module performs a permutation of the first portion of the clock signal.

Claim 41

A frequency hopping generator for use in a wireless communication network, comprising: an XOR processing module having a first input for receiving a first portion of a clock signal and a second input for receiving a selection address, and having an output defining one of a plurality of hop numbers.

Claim 42

A frequency hopping generator for use in a wireless communication network, comprising: an XOR processing module having a first input for receiving a first portion of a clock signal and a second input for receiving a selection address, and having an output defining one of a plurality of hop numbers.