US4876659A
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Pseudo-Random code generator for use with a global positioning system
Assignee: Johns Hopkins University
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Filing: 1988-05-02
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Granted: 1989-10-24
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Expires: 2008-05-02
Abstract
Abstract An apparatus for generating pseudo-random codes is disclosed. The apparatus uniquely stores a set of codes in a memory and uniquely retrieves a particular code sequence. The apparatus has particular application to Global Position Satellite (GPS) earth receivers.
Inventors
- 👤 William S. Devereux
- 👤 Edwin E. Westerfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:58
CPC Classifications
G; G01; G01S; G01S19/00; G01S19/01; G01S19/13; G01S19/24; G01S19/30; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; H; H03; H03K; H03K3/00; H03K3/84; G06F2207/00; G06F2207/58; G06F2207/581
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
154 words
An apparatus for generating a pseudo-random code, comprising: a memory means for storing a set of pseudo-random codes, wherein the memory is allocated into a plurality of memory spaces each one word wide, with each bit in the word containing a bit for a different pseudo-random code, and wherein the length of the memory space is dependent on the length of the pseudo-random codes; a first address means for selecting the memory space containing the desired pseudo-random code; a counter operably coupled to a clock; a second address means operably coupled to said counter to output a data word from the selected memory space of said memory with each clock cycle, where each word contains a bit associated with several possible pseudo-random codes; a multiplexer operably coupled to said memory to select the bit associated with the selected pseudo-random code, whereby sequential bits for the selected pseudo-random code is generated with each clock cycle.
Claim 2
Independent Claim
154 words
An apparatus for generating a pseudo-random code, comprising: a memory means for storing a set of pseudo-random codes, wherein the memory is allocated into a plurality of memory spaces each one word wide, with each bit in the word containing a bit for a different pseudo-random code, and wherein the length of the memory space is dependent on the length of the pseudo-random codes; a first address means for selecting the memory space containing the desired pseudo-random code; a counter operably coupled to a clock; a second address means operably coupled to said counter to output a data word from the selected memory space of said memory with each clock cycle, where each word contains a bit associated with several possible pseudo-random codes; a multiplexer operably coupled to said memory to select the bit associated with the selected pseudo-random code, whereby sequential bits for the selected pseudo-random code is generated with each clock cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-23 | 1993-04-24 | 1993-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-23 | 1997-04-24 | 1997-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-23 | 2001-04-24 | 2001-10-24 | $7700.00 | Window Closed / Lapsed |