US4748576A
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Pseudo-random binary sequence generators
Assignee: L'ETAT FRANCAIS REPRESENTE PAR LE MINISTRE DE PTT
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Filing: 1985-02-04
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Granted: 1988-05-31
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Expires: 2005-02-04
Abstract
Abstract A pseudo-random binary sequence generator comprises at least one shift register (S, T) arranged in a recirculating loop and having a plurality of logic gates (G) for logically combining the outputs of selected stages of the register to provide a pseudo-random sequence, and a multiplexer (M), having a p data inputs and q address inputs all connected to selected shift register stages, and which selects at any instant one of the p data input bits in accordance with the q-bit address word to provide the generator output. The number s of logic gates is especially high and is related to the total number r of shift register stages (r>p+q) by the expression: 2 s ≧r 2 . Some of the shift register stages of the or each shift register are connected to selected data inputs of the multiplexer and others of the stages of the same shift register are connected to selected address inputs of the multiplexer. Switches (SW1-SW4) are provided for regularly loading a re-initialization word into the shift register(s), and this re-initialization word can be formed by an arrangement (FIG. 4) which combines a control word with the frame count.
Inventors
- 👤 Henry J. Beker
- 👤 Luc Emiel L. Boes
- 👤 Peter R. Brennand
- 👤 Edmund R. Brown
- 👤 Gerald O. Crowther
- 👤 Wilhelmus M. Dorn
- 👤 Stanley M. Edwardson
- 👤 Stephen R. Ely
- 👤 Louis C. Guillou
- 👤 Peter M. Jenner
- 👤 Sylvia M. Jennings
- 👤 Michael J. Knee
- 👤 Arthur G. Mason
- 👤 Jean-Marie C. Nicolas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; H04; H04N; H04N7/00; H04N7/16; H04N7/167; H04N7/1675
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
126 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means having a total of r stages and having s logic gates located between register stages for logically combining the outputs of selected stages to provide a pseudo-random sequence; and means connecting the p data input of the selector means to the outputs of selected shift register stages and for connecting the q address inputs of the selector means to the outputs of q selected shift register stages, in which r and s are so chosen that: r>p+q and 2.sup.s ≧r.sup.2.
Claim 2
Dependent Claim
126 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means having a total of r stages and having s logic gates located between register stages for logically combining the outputs of selected stages to provide a pseudo-random sequence; and means connecting the p data input of the selector means to the outputs of selected shift register stages and for connecting the q address inputs of the selector means to the outputs of q selected shift register stages, in which r and s are so chosen that: r>p+q and 2.sup.s ≧r.sup.2.
Claim 3
Dependent Claim
18 words
A generator according to claim 1, in which the number of stages r is so chosen that: r≧p+q.sup.2.
Claim 4
Dependent Claim
64 words
A generator according to claim 1, in which the shift register means comprises at least one recirculating loop and the connecting means connects the outputs of some of the shift register stages of the said loop to data inputs of the selector means and the outputs of others of the shift register stages of the same loop to address inputs of the selector means.
Claim 5
Dependent Claim
19 words
A generator according to claim 3, including means for regularly loading a re-initialisation word into the shift register means.
Claim 6
Dependent Claim
118 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means comprising at least one recirculating loop having a plurality of logic gates for logically combining the outputs of selected stages of the loop to provide a pseudo-random sequence; and means connecting the outputs of some of the shift register stages of the said loop to data inputs of the selector means and the outputs of others of the shift register stages of the same loop to address inputs of the selector means.
Claim 7
Dependent Claim
118 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means comprising at least one recirculating loop having a plurality of logic gates for logically combining the outputs of selected stages of the loop to provide a pseudo-random sequence; and means connecting the outputs of some of the shift register stages of the said loop to data inputs of the selector means and the outputs of others of the shift register stages of the same loop to address inputs of the selector means.
Claim 8
Dependent Claim
48 words
A generator according to claim 5, in which the recirculatory shift register means comprises two recirculating loops, respective ones of the data inputs of the selector means being connected to each loop, and respective ones of the address inputs of the selector means being connected to each loop.
Claim 9
Dependent Claim
125 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means comprising at least one recirculating loop having a plurality of logic gates for logically combining the outputs of selected stages of the loop to provide a pseudo-random sequence; means connecting the p data inputs of the selector means to the outputs of selected shift register stages and for connecting the q address inputs of the selector means to the outputs of q selected shift register stages; and means for regularly loading a re-initialisation word into the shift register means.
Claim 10
Dependent Claim
125 words
A pseudo-random binary sequence generator, comprising: selector means having p data inputs and q address inputs (2 q ≧p) for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output; recirculatory shift register means comprising at least one recirculating loop having a plurality of logic gates for logically combining the outputs of selected stages of the loop to provide a pseudo-random sequence; means connecting the p data inputs of the selector means to the outputs of selected shift register stages and for connecting the q address inputs of the selector means to the outputs of q selected shift register stages; and means for regularly loading a re-initialisation word into the shift register means.
Claim 11
Dependent Claim
50 words
A generator according to claim 7, wherein the loading means comprises: means for generating a periodic count word; means for generating a control word; and means for combining the count and control words whereby to alter the re-initialisation word every time it is regularly loaded into the shift register means.
Claim 12
Dependent Claim
19 words
A generator according to claim 8, in which the combining means comprise a circuit for complementing alternate count words.
Claim 13
Dependent Claim
27 words
A generator according to claim 8, in which the combining means comprises modulo-2 adding means for adding each count word to selected bits of the control word.
Claim 14
Dependent Claim
23 words
A generator according to claim 8, in which the periodic count word is a frame count word formed by counting successive video frames.
Claim 15
Dependent Claim
35 words
A generator according to claim 7, further including means operative subsequent to the loading of a re-initialisation word to clock the register means for a plurality of clock cycles before the generator output is utilised.
Claim 16
Dependent Claim
42 words
A generator according to claim 7, in which the recirculatory shift register means is arranged in normal operation in two recirculating loops, and the loading means when operated connects the shift register means of the two loops into a single shift register.
References Cited (Backward Citations)
US3881099A
Cited
US4047008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |