US3881099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pseudo-random binary sequence generator
Assignee: LANNIONAISE D'ELECTRONIQUE SLE-CITEREL Ste
•
Filing: 1973-12-17
•
Granted: 1975-04-29
•
Expires: 1993-12-17
Abstract
Abstract The invention comes within the branch of equipment used for controlling digital operation systems, for example, pulse code modulation telephonic transmission systems. It concerns a random sequence generator operating at a frequency which is a multiple of the frequency of a generator of known type, comprising a time multiplexer in functional connection with the said generator of known type. It is used in services for the studying and maintenance of digital operation systems.
Inventors
- 👤 Claude Ailett
- 👤 Jacques Bigou
- 👤 Yves Bretecher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:50
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
A binary sequence generator comprising counter means including a plural stage shift register for effecting a cyclic counting at a frequency F, a first sum modulo 2 circuit connected between one pair of stages of said shift register and being also connected to the output of the last stage of said shift register, a second sum modulo 2 circuit having inputs connected to the outputs of other stages of said shift register than those connected to said first sum modulo 2 circuit, and a time multiplexer connected to the output of said second sum modulo 2 circuit and the output of the first stage of said shift register and receiving a multiplexing signal.
Claim 2
Dependent Claim
113 words
A binary sequence generator comprising counter means including a plural stage shift register for effecting a cyclic counting at a frequency F, a first sum modulo 2 circuit connected between one pair of stages of said shift register and being also connected to the output of the last stage of said shift register, a second sum modulo 2 circuit having inputs connected to the outputs of other stages of said shift register than those connected to said first sum modulo 2 circuit, and a time multiplexer connected to the output of said second sum modulo 2 circuit and the output of the first stage of said shift register and receiving a multiplexing signal.
Claim 3
Dependent Claim
28 words
A binary sequence generator as defined in claim 1, wherein said first sum modulo 2 circuit is connected between the third and fourth stage of said shift register.
Claim 4
Dependent Claim
31 words
A binary sequence generator as defined in claim 2, wherein said second sum modulo 2 circuit receives inputs from the outputs of the second and seventh stages of said shift register.
Claim 5
Dependent Claim
22 words
A binary sequence generator as defined in claim 3, wherein the multiplexing signal applied to said time multiplexer has a frequency 2F.
Claim 6
Dependent Claim
41 words
A binary sequence generator as defined in claim 3, further including a third sum modulo 2 circuit having inputs connected to the outputs of the third and ninth stages of said shift register and an output connected to said time multiplexer.
Claim 7
Dependent Claim
41 words
A binary sequence generator as defined in claim 5, further including a fourth sum modulo 2 circuit having inputs connected to the outputs of the first and tenth stages of said shift register and an output connected to said time multiplexer.
Claim 8
Dependent Claim
22 words
A binary sequeNce generator as defined in claim 6, wherein the multiplexing signal applied to said time multiplexer has a frequency 4F.
Claim 9
Dependent Claim
126 words
A binary sequence generator comprising counter means for effecting a cyclic counting at a frequency F, including a plural stage shift register in which the output of each stage is connected to the input of the second succeeding stage; a first sum molulo 2 circuit inserted into one connection between stages and having an input connected to the input of the first stage of said shift register; a second sum modulo 2 circuit connected between other stages of said shift register than those to which said first sum modulo 2 circuit is connected and having an input connected to the last stage of said shift register; and a time multiplexer having inputs connected to two adjacent stages of said shift register and receiving a multiplexing signal.
Claim 10
Dependent Claim
126 words
A binary sequence generator comprising counter means for effecting a cyclic counting at a frequency F, including a plural stage shift register in which the output of each stage is connected to the input of the second succeeding stage; a first sum molulo 2 circuit inserted into one connection between stages and having an input connected to the input of the first stage of said shift register; a second sum modulo 2 circuit connected between other stages of said shift register than those to which said first sum modulo 2 circuit is connected and having an input connected to the last stage of said shift register; and a time multiplexer having inputs connected to two adjacent stages of said shift register and receiving a multiplexing signal.
Claim 11
Dependent Claim
28 words
A binary sequence generator as defined in claim 8, wherein said first sum modulo 2 circuit is connected between the second and fourth stages of said shift register.
Claim 12
Dependent Claim
28 words
A binary sequence generator as defined in claim 9, wherein said second sum modulo 2 circuit is connected between the third and fifth stages of said shift register.
Claim 13
Dependent Claim
22 words
A binary sequence generator as defined in claim 10, wherein the multiplexing signal applied to said time multiplexer has a frequency 2F.
Claim 14
Dependent Claim
159 words
A binary sequence generator comprising counter means for effecting a cyclic counting at a frequency F, including a plural stage shift register in which the output of each stage is connected to the input of the third succeeding stage; a first sum molulo 2 circuit inserted into one connection between stages and having an input connected to the input of the first stage of said shift register; a second sum modulo 2 circuit connected between other stages of said shift register than those to which said first sum modulo 2 circuit is connected and having an input connected to the last stage of said shift register; a third sum modulo 2 circuit connected between still other stages of said shift register and having an input connected to the output of the next to last stage of said shift register; and a time multiplexer having inputs connected to three adjacent stages of said shift register and receiving a multiplexing signal.
Claim 15
Dependent Claim
159 words
A binary sequence generator comprising counter means for effecting a cyclic counting at a frequency F, including a plural stage shift register in which the output of each stage is connected to the input of the third succeeding stage; a first sum molulo 2 circuit inserted into one connection between stages and having an input connected to the input of the first stage of said shift register; a second sum modulo 2 circuit connected between other stages of said shift register than those to which said first sum modulo 2 circuit is connected and having an input connected to the last stage of said shift register; a third sum modulo 2 circuit connected between still other stages of said shift register and having an input connected to the output of the next to last stage of said shift register; and a time multiplexer having inputs connected to three adjacent stages of said shift register and receiving a multiplexing signal.
Claim 16
Dependent Claim
28 words
A binary sequence generator as defined in claim 12, wherein said first sum modulo 2 circuit is connected between the first and fourth stages of said shift register.
Claim 17
Dependent Claim
28 words
A binary sequence generator as defined in claim 13, wherein said second sum modulo 2 circuit is connected between the third and sixth stages of said shift register.
Claim 18
Dependent Claim
28 words
A binary sequence generator as defined in claim 14, wherein said third sum modulo 2 circuit is connected between the second and fifth stages of said shift register.
Claim 19
Dependent Claim
22 words
A binary sequence generator as defined in claim 15, wherein the multiplexing signal applied to said time multiplexer has a frequency 3F.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-28 | 1978-10-28 | 1979-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-28 | 1982-10-28 | 1983-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-28 | 1986-10-28 | 1987-04-29 | $7700.00 | Window Closed / Lapsed |