US6098169A
Expired / Lapsed
US
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Thread performance analysis by monitoring processor performance event registers at thread switch
Assignee: Intel Corp
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Filing: 1997-12-23
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Granted: 2000-08-01
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Expires: 2017-12-23
Abstract
Abstract A thread switch handler is provided which monitors performance characteristics of a processor executing instructions from two or more threads of an application. The thread switch handler detects when the processor has switched between a first and second thread and is capable of reading the performance registers available in many commercial processors at or about that time. The data that is read from the performance registers at each thread switch represents performance characteristics of the processor on a per-thread basis.
Inventors
- 👤 Kumar Ranganathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F2201/00; G06F2201/865
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
93 words
An apparatus for monitoring processor performance characteristics comprising: a processor adapted to execute first and second threads where each of said first and second threads includes a series of instructions, said processor including at least one performance register adapted to record at least one occurrence of a processor event; and a thread switch handler adapted to detect when said processor switches between execution of said first thread and said second thread and adapted to monitor the performance register of said processor to identify said processor event with the execution of said first thread.
Claim 2
Independent Claim
93 words
An apparatus for monitoring processor performance characteristics comprising: a processor adapted to execute first and second threads where each of said first and second threads includes a series of instructions, said processor including at least one performance register adapted to record at least one occurrence of a processor event; and a thread switch handler adapted to detect when said processor switches between execution of said first thread and said second thread and adapted to monitor the performance register of said processor to identify said processor event with the execution of said first thread.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1 wherein said thread switch handler is adapted to transfer a data value from said register to a performance monitor application.
Claim 4
Dependent Claim
24 words
The apparatus of claim 1 wherein said thread switch handler is adapted to receive an identifier for each of said first and second threads.
Claim 5
Dependent Claim
49 words
The apparatus of claim 1 wherein said first thread is part of a first process and said second thread is part of a second process, and said thread switch handler is further adapted to detect when said processor switches between execution of said first process and said second process.
Claim 6
Independent Claim
155 words
An apparatus for monitoring processor performance characteristics comprising: a processor adapted to execute first and second threads where each of said first and second threads includes a series of instructions, said processor including at least one performance register adapted to record at least one occurrence of a processor event; and a thread switch handler adapted to detect when said processor switches between execution of said first thread and said second thread and adapted to monitor the performance register of said processor to identify said processor event with the execution of said first thread; said thread switch handler is adapted to receive an identifier for each of said first and second threads and said thread switch handler is adapted to store data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 7
Independent Claim
155 words
An apparatus for monitoring processor performance characteristics comprising: a processor adapted to execute first and second threads where each of said first and second threads includes a series of instructions, said processor including at least one performance register adapted to record at least one occurrence of a processor event; and a thread switch handler adapted to detect when said processor switches between execution of said first thread and said second thread and adapted to monitor the performance register of said processor to identify said processor event with the execution of said first thread; said thread switch handler is adapted to receive an identifier for each of said first and second threads and said thread switch handler is adapted to store data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 8
Dependent Claim
42 words
The apparatus of claim 5 wherein incrementing the data value in the storage area for said first thread based on said performance register causes the data value in the storage area for the first process to be incremented in a like manner.
Claim 9
Dependent Claim
21 words
The apparatus of claim 5 wherein said processor includes a time stamp counter performance register and an event counter performance register.
Claim 10
Dependent Claim
31 words
The apparatus of claim 5 wherein thread switch handler detects when said processor switch between execution of said first thread and said second thread via the operation of an operating system.
Claim 11
Independent Claim
101 words
A method for monitoring processor performance characteristics comprising: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; and monitoring said performance register of said processor to identify said processor event with the execution of said first thread.
Claim 12
Independent Claim
101 words
A method for monitoring processor performance characteristics comprising: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; and monitoring said performance register of said processor to identify said processor event with the execution of said first thread.
Claim 13
Dependent Claim
19 words
The method of claim 9 further comprising: transferring a data value from said register to a performance monitor application.
Claim 14
Dependent Claim
23 words
The method of claim 9 further comprising: receiving an identifier for each of said first and second threads at said thread switch handler.
Claim 15
Dependent Claim
44 words
The method of claim 9 wherein said first thread is part of a first process and said second thread is part of a second process, the method further comprising: detecting when said processor switches between execution of said first process and said second process.
Claim 16
Independent Claim
153 words
A method for monitoring processor performance characteristics comprising: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; receiving an identifier for each of said first and second threads at said thread switch handler; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; monitoring said performance register of said processor to identify said processor event with the execution of said first thread; and storing data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 17
Independent Claim
153 words
A method for monitoring processor performance characteristics comprising: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; receiving an identifier for each of said first and second threads at said thread switch handler; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; monitoring said performance register of said processor to identify said processor event with the execution of said first thread; and storing data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 18
Dependent Claim
41 words
The method of claim 13 further comprising: incrementing the data value in the storage area for said first thread based on said performance register; and incrementing the data value in the storage area for the first process in a like manner.
Claim 19
Dependent Claim
21 words
The method of claim 13 wherein said processor includes a time stamp counter performance register and an event counter performance register.
Claim 20
Dependent Claim
31 words
The method of claim 13 wherein thread switch handler detects when said processor switches between execution of said first thread and said second thread via the operation of an operating system.
Claim 21
Dependent Claim
128 words
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for monitoring processor performance characteristics, the method comprising the steps of: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; and monitoring said performance register of said processor to identify said processor event with the execution of said first thread.
Claim 22
Dependent Claim
128 words
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for monitoring processor performance characteristics, the method comprising the steps of: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; detecting, via a thread switch handler, said switching from execution of said first thread to said second thread by said processor; and monitoring said performance register of said processor to identify said processor event with the execution of said first thread.
Claim 23
Dependent Claim
32 words
The set of instructions of claim 17, wherein the execution of said set of instructions further comprises the step of: transferring a data value from said register to a performance monitor application.
Claim 24
Dependent Claim
36 words
The set of instructions of claim 17, wherein the execution of said set of instructions further comprises the step of: receiving an identifier for each of said first and second threads at said thread switch handler.
Claim 25
Dependent Claim
55 words
The set of instructions of claim 17, wherein said first thread is part of a first process and said second thread is part of a second process, and the execution of said set of instructions further comprises the step of: detecting when said processor switches between execution of said first process and said second process.
Claim 26
Dependent Claim
180 words
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for monitoring processor performance characteristics, the method comprising the steps of: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; receiving an identifier for each of said first and second threads at said thread switch handler; detecting, via a thread switch handier, said switching from execution of said first thread to said second thread by said processor; monitoring said performance register of said processor to identify said processor event with the execution of said first thread; and storing data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 27
Dependent Claim
180 words
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for monitoring processor performance characteristics, the method comprising the steps of: executing a series of instructions of a first thread by a processor; recording at least one occurrence of a processor event in a performance register; switching from execution of said first thread by said processor to execution of a second thread by said processor, said second thread including a series of instructions; receiving an identifier for each of said first and second threads at said thread switch handler; detecting, via a thread switch handier, said switching from execution of said first thread to said second thread by said processor; monitoring said performance register of said processor to identify said processor event with the execution of said first thread; and storing data values from said register in a thread tree data structure, where said thread tree data structure includes a storage area for each of said first and second threads and said first and second processes.
Claim 28
Dependent Claim
54 words
The set of instructions of claim 21, wherein the execution of said set of instructions further comprises the steps of: incrementing the data value in the storage area for said first thread based on said performance register; and incrementing the data value in the storage area for the first process in a like manner.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |