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Patent US6096092A successfully refreshed from Google Patents.
US6096092A
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Automatic synthesizing method for logic circuits
Assignee: Panasonic Holdings Corp
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Filing: 1998-04-06
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Granted: 2000-08-01
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Expires: 2018-04-06
Abstract
Abstract Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation sigma med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn)x sigma med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value. Then, by using a virtual wiring model including the defined line length WL(fn), the logic circuits are automatically synthesized, and a net list resulting from the synthesis is used for generating a layout of the logic circuits.
Inventors
- 👤 Miwaka Takahashi
- 👤 Masahiko Toyonaga
- 👤 Yoshihiro Seko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:28
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
105 words
An automatically synthesizing method for a large number of logic circuits included in a semiconductor LSI comprising: a representative line length extraction processing for selecting a line length of one line among plural lines connecting said logic circuits as a representative line length; a defined line length determination processing for obtaining a short line length as line redundancy in consideration of distribution of line lengths of said plural lines, and obtaining a defined line length by adding said short line length to said representative line length; and a logic circuit automatic synthesis processing for automatically synthesizing said logic circuits by using said defined line length.
Claim 2
Dependent Claim
105 words
An automatically synthesizing method for a large number of logic circuits included in a semiconductor LSI comprising: a representative line length extraction processing for selecting a line length of one line among plural lines connecting said logic circuits as a representative line length; a defined line length determination processing for obtaining a short line length as line redundancy in consideration of distribution of line lengths of said plural lines, and obtaining a defined line length by adding said short line length to said representative line length; and a logic circuit automatic synthesis processing for automatically synthesizing said logic circuits by using said defined line length.
Claim 3
Dependent Claim
61 words
The automatically synthesizing method of claim 1, wherein, in said logic circuit automatically synthesis processing, a net list corresponding to connections between said synthesized logic circuits is output, and said automatically synthesizing method is further provided with a layout automatically generation processing for inputting said net list and a macro cell library and generating a layout of said synthesized logic circuits.
Claim 4
Dependent Claim
27 words
The automatically synthesizing method of claim 1, wherein said representative line length is selected with regard to each fanout number in said representative line length extraction processing.
Claim 5
Dependent Claim
38 words
The automatically synthesizing method of claim 1 or 3, wherein said representative line length is selected on the basis of plural lines obtained through actual layout of said synthesized logic circuits in said representative line length extraction processing.
Claim 6
Dependent Claim
60 words
The automatically synthesizing method of claim 4, wherein said plural lines obtained through the actual layout of said synthesized logic circuits are aligned in the order of lengths thereof and a median line length corresponding to a line length of a line positioned at a center is selected as said representative line length in said representative line length extraction processing.
Claim 7
Dependent Claim
69 words
The automatically synthesizing method of claim 5, wherein, among said plural lines actually experimentally laid out, one line included in a predetermined range between said median line length and a larger line length is selected, and a difference between a length of said selected one line and said median line length is defined as said short line length as the line redundancy in said defined line length determination processing.
Claim 8
Dependent Claim
35 words
The automatically synthesizing method of claim 1 or 3, wherein said representative line length is estimated by using an expression without actually experimentally laying out said logic circuits in said representative line length extraction processing.
Claim 9
Dependent Claim
33 words
The automatically synthesizing method of claim 7, wherein said expression used in said representative line length extraction processing includes information obtainable from a net list obtained by previously automatically synthesizing said logic circuits.
Claim 10
Dependent Claim
24 words
The automatically synthesizing method of claim 8, wherein said information obtainable from said net list includes a total number of nets and fanout numbers.
Claim 11
Dependent Claim
53 words
The automatically synthesizing method of claim 7, wherein said representative line length estimated by using said expression in said representative line length extraction processing corresponds to a median line length that is a length of a line positioned at a center when said plural lines are aligned in the order of lengths thereof.
Claim 12
Dependent Claim
27 words
The automatically synthesizing method of claim 10, wherein said expression used in said representative line length extraction processing includes an average line length of said plural lines.
Claim 13
Dependent Claim
60 words
The automatically synthesizing method of claim 11, wherein said expression used in said representative line length extraction processing is: WLmed(fn)=M1*WLave(fn)/(fn.sup.M2 *N.sup.M3)+M4*WLave(fn)/N.sup.M3 wherein fn indicates a fanout number, WLmed(fn) indicates a median line length of each fanout number, WLave(fn) indicates an average line length of each fanout number, N indicates a total number of nets, and M1 through M4 indicate constants.
Claim 14
Dependent Claim
44 words
The automatically synthesizing method of claim 1 or 3, wherein said short line length as the line redundancy used in said representative line length extraction processing is obtained by multiplying a standard deviation of said lines and a probability coefficient of said standard deviation.
Claim 15
Dependent Claim
60 words
The automatically synthesizing method of claim 13, wherein said standard deviation of said lines is calculated based on a median line length obtained by arranging a plurality of lines provided in an actual layout in order of length and selecting one of said plurality of lines which is positioned in the middle of said arrangement of said plurality of lines.
Claim 16
Dependent Claim
57 words
The automatically synthesizing method of claim 14, wherein said standard deviation is obtained by the following expression: σmed(fn)=S1*WLmed(fn)*(N.sup.S2 /fn).sup.S3 wherein fn indicates a fanout number, σmed(fn) indicates a standard deviation of each fanout number, WLmed(fn) indicates a median line length of each fanout number, N indicates a total number of nets, and S1 through S3 indicate constants.
Claim 17
Dependent Claim
26 words
The automatically synthesizing method of claim 13, wherein said probability coefficient is calculated on the basis of a fanout number and a total number of nets.
Claim 18
Dependent Claim
47 words
The automatically synthesizing method of claim 16, wherein said probability coefficient is obtained by the following expression: K(fn)=K1*1/(fn.sup.K2 *N.sup.K3)+K4/N.sup.K3 wherein fn indicates a fanout number, K(fn) indicates a probability coefficient of each fanout number, N indicates a total number of nets, and K1 through K4 indicate constants.
Claim 19
Dependent Claim
73 words
The automatically synthesizing method of claim 1 or 3, wherein said defined line length is obtained by the following expression in said defined line length determination processing: WL(fn)=WLmed(fn)+K(fn)·σmed(fn) wherein fn indicates a fanout number, WL(fn) indicates a defined line length of each fanout number, WLmed(fn) indicates a median line length of each fanout number, K(fn) indicates a probability coefficient of each fanout number, and σmed(fn) indicates a standard deviation of each fanout number.
Claim 20
Dependent Claim
24 words
The automatically synthesizing method of claim 13, wherein said probability coefficient is varied in accordance with a requirement in design of said semiconductor LSI.
Claim 21
Dependent Claim
35 words
The automatically synthesizing method of claim 19, wherein said probability coefficient is varied to a smaller value when there is a requirement in the design of said semiconductor LSI for attaining a high operation speed.
Claim 22
Dependent Claim
39 words
The automatically synthesizing method of claim 19, wherein said probability coefficient is varied to a larger value when there is a requirement in the design of said semiconductor LSI for completing the design in a short period of time.
References Cited (Backward Citations)
US5187668A
Cited
US5311443A
Cited
JPH06196561A
Cited
US5475607A
Cited
US5737237A
Cited
US5724251A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |