US6096091A
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US
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Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
Assignee: GlobalFoundries Inc
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Filing: 1998-02-24
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Granted: 2000-08-01
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Expires: 2018-02-24
Abstract
Abstract An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit. One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks. The buffers isolate the plurality of reconfigurable logic networks from one another. The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers. The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network. The integrated circuit may also comprise a local memory. The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor. A logic configuration library may also be comprised on the integrated circuit. The logic configuration library is coupled to the embedded processor and is further coupled to the configuration control network. The logic configuration library is operable to store one more configurations for the plurality of reconfigurable logic networks. The reconfigurable logic networks preferably include at least a first logic network and a second logic network.
Inventors
- 👤 Alfred C. Hartmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:33
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F9/00; G06F9/06; G06F9/30; G06F9/30181
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
127 words
An integrated circuit, the integrated circuit comprising: a plurality of reconfigurable logic networks comprised on said integrated circuit; one or more buffers comprised on said integrated circuit, wherein said one or more buffers are coupled between said plurality of reconfigurable logic networks, wherein said one or more buffers isolate said plurality of reconfigurable logic networks from each other to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network comprised on said integrated circuit, wherein said configuration control network is coupled to each of said plurality of reconfigurable logic networks; and an embedded processor comprised on said integrated circuit, wherein said embedded processor is operable to reconfigure one or more of said plurality of reconfigurable logic networks over said configuration control network.
Claim 2
Dependent Claim
127 words
An integrated circuit, the integrated circuit comprising: a plurality of reconfigurable logic networks comprised on said integrated circuit; one or more buffers comprised on said integrated circuit, wherein said one or more buffers are coupled between said plurality of reconfigurable logic networks, wherein said one or more buffers isolate said plurality of reconfigurable logic networks from each other to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network comprised on said integrated circuit, wherein said configuration control network is coupled to each of said plurality of reconfigurable logic networks; and an embedded processor comprised on said integrated circuit, wherein said embedded processor is operable to reconfigure one or more of said plurality of reconfigurable logic networks over said configuration control network.
Claim 3
Dependent Claim
39 words
The integrated circuit of claim 1, further comprising: a local memory comprised on said integrated circuit, wherein said local memory is coupled to said embedded processor, wherein said memory is operable to store data accessible by said embedded processor.
Claim 4
Dependent Claim
47 words
The integrated circuit of claim 1, wherein said embedded processor is operable to calculate a new configuration for said plurality of reconfigurable logic networks, wherein said embedded processor is further operable to reconfigure one or more of the plurality of reconfigurable logic networks with said new configuration.
Claim 5
Dependent Claim
61 words
The integrated circuit of claim 3, further comprising: a logic configuration library comprised on said integrated circuit, wherein said logic configuration library is coupled to said embedded processor, wherein said logic configuration library is further coupled to said configuration control network, wherein said logic configuration library is operable to store one or more configurations for said plurality of reconfigurable logic networks.
Claim 6
Dependent Claim
32 words
The integrated circuit of claim 4, wherein said embedded processor is further operable to save said new configuration in said logic configuration library after said embedded processor has processed said new configuration.
Claim 7
Dependent Claim
24 words
The integrated circuit of claim 4, wherein said logic configuration library stores a pre-compiled collection of configurations for said plurality of reconfigurable logic networks.
Claim 8
Dependent Claim
54 words
The integrated circuit of claim 4, wherein said embedded processor is further operable to select one of said pre-compiled collection of configurations, wherein said embedded processor is further operable to reconfigure one or more of said plurality of reconfigurable logic networks in response to said selection of one of said pre-compiled collection of configurations.
Claim 9
Dependent Claim
32 words
The integrated circuit of claim 1, wherein said plurality of reconfigurable logic networks are configured as a pipeline processor, wherein said plurality of reconfigurable logic networks comprise stages of said pipeline processor.
Claim 10
Dependent Claim
17 words
The integrated circuit of claim 1, wherein said one or more buffers are fall-through first-in first-out buffers.
Claim 11
Dependent Claim
22 words
The integrated circuit of claim 1, wherein each of the plurality of reconfigurable logic networks is defined by a programmable array logic.
Claim 12
Dependent Claim
23 words
The integrated circuit of claim 1, wherein said plurality of reconfigurable logic networks are each operable to clock independently on different clock signals.
Claim 13
Independent Claim
223 words
A method for operating an integrated circuit, wherein said integrated circuit includes a plurality of reconfigurable logic networks including a first logic network and a second logic network, one or more buffers coupled between said plurality of reconfigurable logic networks, a configuration control network coupled to each of said plurality of reconfigurable logic networks, and an embedded processor coupled to said configuration control network, the method comprising: said embedded processor determining a desired configuration for said plurality of reconfigurable logic networks; said embedded processor configuring said plurality of reconfigurable logic networks over said configuration control network; said first logic network receiving a first input; said first logic network operating on said first input to produce a first output; said first logic network transferring said first output to a respective one of said one or more buffers coupled between said plurality of reconfigurable logic networks, wherein said respective one is coupled between said first logic network and said second logic network; said respective one holding said first output until said second logic network is ready to be accepting said first output as a second input; said respective one transferring said first output to said second logic network as said second input; said second logic network operating on said second input to produce a second output; and said second logic network outputting said second output.
Claim 14
Independent Claim
223 words
A method for operating an integrated circuit, wherein said integrated circuit includes a plurality of reconfigurable logic networks including a first logic network and a second logic network, one or more buffers coupled between said plurality of reconfigurable logic networks, a configuration control network coupled to each of said plurality of reconfigurable logic networks, and an embedded processor coupled to said configuration control network, the method comprising: said embedded processor determining a desired configuration for said plurality of reconfigurable logic networks; said embedded processor configuring said plurality of reconfigurable logic networks over said configuration control network; said first logic network receiving a first input; said first logic network operating on said first input to produce a first output; said first logic network transferring said first output to a respective one of said one or more buffers coupled between said plurality of reconfigurable logic networks, wherein said respective one is coupled between said first logic network and said second logic network; said respective one holding said first output until said second logic network is ready to be accepting said first output as a second input; said respective one transferring said first output to said second logic network as said second input; said second logic network operating on said second input to produce a second output; and said second logic network outputting said second output.
Claim 15
Dependent Claim
60 words
The method of claim 12, wherein said one or more buffers are FIFO buffers, the method further comprising: said respective one holding said first output in the order received from said first logic network; and said respective one transferring said first output to said second logic network as said second input in the order received from said first logic network.
Claim 16
Dependent Claim
34 words
The method of claim 12, wherein said one or more buffers are fall-through buffers, the method further comprising: said transferring occurring without substantial buffering delay in said respective one in response to said accepting.
Claim 17
Dependent Claim
60 words
The method of claim 12, wherein said integrated circuit further includes a logic configuration library coupled to said embedded processor and said configuration control network, wherein said logic configuration library includes a plurality of reusable configurations for said plurality of reconfigurable logic networks, the method further comprising: said embedded processor determining said desired configuration from said plurality of reusable configurations.
Claim 18
Dependent Claim
24 words
The method of claim 15, the method further comprising: said embedded processor storing said desired configuration in said logic configuration library after said determining.
Claim 19
Dependent Claim
211 words
An integrated circuit, the integrated circuit comprising: a plurality of reconfigurable logic networks comprised on said integrated circuit; one or more buffers comprised on said integrated circuit, wherein said one or more buffers are coupled between said plurality of reconfigurable logic networks, wherein said one or more buffers isolate said plurality of reconfigurable logic networks from each other to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network comprised on said integrated circuit, wherein said configuration control network is coupled to each of said plurality of reconfigurable logic networks; an embedded processor comprised on said integrated circuit, wherein said embedded processor is operable to reconfigure one or more of said plurality of reconfigurable logic networks over said configuration control network; a local memory comprised on said integrated circuit, wherein said local memory is coupled to said embedded processor, wherein said memory is operable to store data accessible by said embedded processor; and a logic configuration library comprised on said integrated circuit, wherein said logic configuration library is coupled to said embedded processor, wherein said logic configuration library is further coupled to said configuration control network, wherein said logic configuration library is operable to store one or more configurations for said plurality of reconfigurable logic networks.
Claim 20
Dependent Claim
211 words
An integrated circuit, the integrated circuit comprising: a plurality of reconfigurable logic networks comprised on said integrated circuit; one or more buffers comprised on said integrated circuit, wherein said one or more buffers are coupled between said plurality of reconfigurable logic networks, wherein said one or more buffers isolate said plurality of reconfigurable logic networks from each other to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network comprised on said integrated circuit, wherein said configuration control network is coupled to each of said plurality of reconfigurable logic networks; an embedded processor comprised on said integrated circuit, wherein said embedded processor is operable to reconfigure one or more of said plurality of reconfigurable logic networks over said configuration control network; a local memory comprised on said integrated circuit, wherein said local memory is coupled to said embedded processor, wherein said memory is operable to store data accessible by said embedded processor; and a logic configuration library comprised on said integrated circuit, wherein said logic configuration library is coupled to said embedded processor, wherein said logic configuration library is further coupled to said configuration control network, wherein said logic configuration library is operable to store one or more configurations for said plurality of reconfigurable logic networks.
Claim 21
Dependent Claim
19 words
The integrated circuit of claim 17, wherein said plurality of reconfigurable logic networks are configured as a pipeline processor.
Claim 22
Dependent Claim
17 words
The integrated circuit of claim 17, wherein said one or more buffers are fall-through first-in first-out buffers.
Claim 23
Dependent Claim
22 words
The integrated circuit of claim 17, wherein each of the plurality of reconfigurable logic networks is defined by a programmable array logic.
Claim 24
Dependent Claim
116 words
An integrated circuit, the integrated circuit comprising: means for storing data and instructions; a processing means coupled to said means for storing data and instructions, wherein said processing means is operable to store said data and said instructions in said means for storing data and instructions; a plurality of computing means configured as stages of a pipeline processor; one or more buffering means, wherein each of said one or more buffering means is coupled between two of said plurality of computing means; a networking means for distributing commands from said processing means to said plurality of computing means and said one or more buffering means; and means for storing configurations for said plurality of computing means.
Claim 25
Dependent Claim
116 words
An integrated circuit, the integrated circuit comprising: means for storing data and instructions; a processing means coupled to said means for storing data and instructions, wherein said processing means is operable to store said data and said instructions in said means for storing data and instructions; a plurality of computing means configured as stages of a pipeline processor; one or more buffering means, wherein each of said one or more buffering means is coupled between two of said plurality of computing means; a networking means for distributing commands from said processing means to said plurality of computing means and said one or more buffering means; and means for storing configurations for said plurality of computing means.
Claim 26
Dependent Claim
22 words
The integrated circuit of claim 1, wherein each of the plurality of reconfigurable logic networks is defined by a programmable logic device.
Claim 27
Dependent Claim
23 words
The integrated circuit of claim 1, wherein each of the plurality of reconfigurable logic networks is defined by a field programmable gate array.
Claim 28
Dependent Claim
22 words
The integrated circuit of claim 1, wherein each of the plurality of reconfigurable logic networks is defined by a dynamically reconfigurable logic.
Claim 29
Dependent Claim
22 words
The integrated circuit of claim 1, wherein each of the plurality of reconfigurable logic networks is defined by a dynamically reconfigurable hardware.
Claim 30
Dependent Claim
22 words
The integrated circuit of claim 17, wherein each of the plurality of reconfigurable logic networks is defined by a programmable logic device.
Claim 31
Dependent Claim
23 words
The integrated circuit of claim 17, wherein each of the plurality of reconfigurable logic networks is defined by a field programmable gate array.
Claim 32
Dependent Claim
22 words
The integrated circuit of claim 17, wherein each of the plurality of reconfigurable logic networks is defined by a dynamically reconfigurable logic.
Claim 33
Dependent Claim
22 words
The integrated circuit of claim 17, wherein each of the plurality of reconfigurable logic networks is defined by a dynamically reconfigurable hardware.
Claim 34
Dependent Claim
94 words
An integrated circuit comprising: plurality of reconfigurable logic networks; a data buffer coupled between a pair of the plurality of reconfigurable logic networks to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network coupled to each of said plurality of reconfigurable logic networks; an embedded processor; wherein said embedded processor is operable to calculate a new configuration for one of said plurality of reconfigurable logic networks, wherein said embedded processor is further operable to reconfigure the one of the plurality of reconfigurable logic networks with said new configuration.
Claim 35
Dependent Claim
94 words
An integrated circuit comprising: plurality of reconfigurable logic networks; a data buffer coupled between a pair of the plurality of reconfigurable logic networks to allow for pipelined processing through said plurality of reconfigurable logic networks; a configuration control network coupled to each of said plurality of reconfigurable logic networks; an embedded processor; wherein said embedded processor is operable to calculate a new configuration for one of said plurality of reconfigurable logic networks, wherein said embedded processor is further operable to reconfigure the one of the plurality of reconfigurable logic networks with said new configuration.
Claim 36
Dependent Claim
74 words
The integrated circuit of claim 30 further comprising: a logic configuration library coupled to said embedded processor, wherein said logic configuration library is configured to store one or more configurations for each of said plurality of reconfigurable logic networks; wherein the embedded processor is configured to read a configuration stored therein, and wherein said embedded processor is operable to reconfigure a reconfigurable logic network in accordance with the configuration read from the configuration library.
Claim 37
Independent Claim
114 words
A method for operating an intergrated circuit, wherein said integrated circuit comprises a plurality of reconfigurable logic networks including a first reconfigurable logic network and a second reconfigurable logic network, a data buffer coupled between the first and second reconfigurable logic networks, a configuration control network coupled to each of said plurality of reconfigurable logic networks, and an embedded processor coupled to said configuration control network, the method comprising: said embedded processor manipulating a configuration for a reconfigurable logic network; said embedded processor configuring said first reconfigurable logic network via said configuration control network in accordance with the manipulated configuration to operate as a pipeline stage in conjunction with said second reconfigurable logic network.
Claim 38
Independent Claim
114 words
A method for operating an intergrated circuit, wherein said integrated circuit comprises a plurality of reconfigurable logic networks including a first reconfigurable logic network and a second reconfigurable logic network, a data buffer coupled between the first and second reconfigurable logic networks, a configuration control network coupled to each of said plurality of reconfigurable logic networks, and an embedded processor coupled to said configuration control network, the method comprising: said embedded processor manipulating a configuration for a reconfigurable logic network; said embedded processor configuring said first reconfigurable logic network via said configuration control network in accordance with the manipulated configuration to operate as a pipeline stage in conjunction with said second reconfigurable logic network.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |